PEF 3452 H V1.3 Infineon Technologies, PEF 3452 H V1.3 Datasheet
PEF 3452 H V1.3
Specifications of PEF 3452 H V1.3
PEF3452HV13XP
SP000007643
Related parts for PEF 3452 H V1.3
PEF 3452 H V1.3 Summary of contents
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TE3-LIU™ ...
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... Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body support and/or maintain and sustain and/or protect human life ...
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TE3-LIU™ Revision History: Previous Version: Page Subjects (major changes since last revision) Page 49 Table 17 2005-01-24 Preliminary Data Sheet TE3-LIU V1.3, 2001-12-05, DS1 Rev. 2 wg_template_fm5_a5_2003-09-01.fm / DS4 ...
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Table of Contents Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 4.3 Framer Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 1 Interface Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Preface The PEF 3452 (TE3-LIU™ flexible line interface unit for a wide area of telecommunication and data communication applications. The device is addressed to fulfill all requirements to build a DS3, STS line interface. Organization of ...
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Related Documentation This document refers to the following international standards (in alphabetical/numerical order): ACA TS016 (general requirements for Australia) CTR-24/TBR-24 (E3 requirements) ETS 300 166 (E3 transmit return loss) ITU-T G.703 (E3 pulse mask, B3ZS/HDB3 code, E3 receive return loss) ...
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Overview The TE3-LIU™ PEF 3452 Line Interface Unit is used to connect a DS3/STS framer device to an analog transmission line. The line interface fulfills the relevant standards for DS3 (44.736 Mbit/s), STS-1 (51.840 Mbit/s) and E3 ...
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Line Interface Unit for DS3, STS1 and E3 TE3-LIU™ Version 1.3 1.1 Features • Generic analog interface for all DS3/STS-1/E3 applications • Single chip solution for receive and transmit direction • 3.3 V low power device • Integrated receive equalization ...
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Hardware Interface Mode • DS3/STS • Line Coding (E3: HDB3 or AMI; DS3/STS-1: B3ZS or AMI) • Transmitter disable • Power down • Remote loop • Local loop • Single/dual rail operation • Receive clock edge selection • ...
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Logic Symbol RL1 RL2 XTAL1 XTAL2 XL1 XL2 Figure 1 Logic Symbol Data Sheet PEF 3452 TM TE3-LIU HW + µP Access 13 PEF 3452 TE3-LIU V1.3 Overview RDOP RDON/BPV RCLK LOS XDIP XDIN XCLK F0229 Rev. 2, 2005-01-24 ...
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Typical Applications Figure 2 to Figure 4 show typical applications using the TE3-LIU™. DS3 TE3_LIU analog Figure 2 T3/T1 Multiplexer Application DS3 analog Figure 3 Channelized T3 Link Layer Application DS3 analog Figure 4 Unchannelized T3 Link Layer Application ...
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Note: TE3-MUX (PEB 3445 M13 MUltipleXer/demultiplexer with an integrated DS3 framer ™ QuadLIU (PEB 22504 4-channel Line Interface Unit for E1/T1/J1 ™ DSCC4 (PEB 20534 4-channel Serial Communication Controller ™ TE3-CHATT (PEB 3456) ...
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Pin Descriptions 2.1 Pin Diagram TRS TDI TMS VDDXP XTAL2 XTAL1 VSSXP TCK TDO JATT VDDX Figure 5 Pin Configuration Data Sheet P-MQFP-44-2 (top view PEF 3452 TM TE3-LIU ...
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Pin Definitions and Functions Table 1 Interface Pin Functions Pin No. Symbol Receive Direction 9 RL1 10 RL2 25 RDOP 24 RDON BPV 26 RCLK Data Sheet Input (I) Function Output (O) Supply (S) I (analog) Line Receiver 1 ...
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Table 1 Interface Pin Functions (cont’d) Pin No. Symbol Transmit Direction 1 XL1 3 XL2 31 XDIP 32 XDIN 30 XCLK Data Sheet Input (I) Function Output (O) Supply (S) O (analog) Transmit Line 1 (transmit bipolar ring) Analog output ...
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Table 1 Interface Pin Functions (cont’d) Pin No. Symbol Global Clock Reference 29 REFCLK 39 XTAL1 38 XTAL2 Data Sheet Input (I) Function Output (O) Supply (S) I Reference Clock REFCLK is the basic internal clock. It must be stable ...
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Table 2 Control Pin Functions Pin No. Symbol 33 RES DS3/E3 4 DS3/STS-1 13 LCODE 16 XAIS Data Sheet Input (I) Function Output (O) Supply (S) I Hardware Reset A low signal at this pin forces the ...
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Table 2 Control Pin Functions (cont’d) Pin No. Symbol XLT 14 MON 15 BLE 12 DR/SR 6 RPE 7 XPE Data Sheet Input (I) Function Output (O) Supply ( Remote Loop Switching ...
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Table 2 Control Pin Functions (cont’d) Pin No. Symbol 43 JATT 22 LOS 1) If RL=LL=1, the device is set into power down mode. Data Sheet Input (I) Function Output (O) Supply ( Jitter Attenuation Enable This ...
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Table 3 Power Supply Pins Pin No. Symbol 11 V DDR 8 V SSR 44 V DDX 2 V SSX 18 V DDRP 17 V SSRP 37 V DDXP 40 V SSXP Data Sheet ...
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Table 4 Test Pins Pin No. Symbol 34 TRS 35 TDI 36 TMS 41 TCK 42 TDO 1) These pins are used for factory test only; boundary scan mode is not provided. Note input or input/output comprising ...
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Functional Description 3.1 Functional Overview The TE3-LIU™ device contains analog and digital functional blocks, which are configured and controlled by direct hardware or microprocessor control. The main interfaces are • Receive Line Interface • Transmit Line Interface • Framer ...
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Block Diagram Figure 6 Block Diagram Data Sheet Functional Description 26 PEF 3452 TE3-LIU V1.3 TRS TCK TMS TDI TDO RES REFCLK DS3/E3 DS3/STS-1 JATT XAIS LCODE XPE RPE XLT MON LL RL DR/SR BLE CS LOS Rev. 2, ...
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Functional Blocks 3.3.1 Hardware Control Unit All hardware control signals except DS3/E3, DS3/STS-1 and JATT are gated by CS. All other control signals are gated allow an easy connection to a microprocessor (µP) data bus. DS3/E3, ...
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Table 5 Hardware Control Functions (cont’d) Device Function Select remote loop Select local loop Select power down mode Blanking enable Line monitoring mode Transmitter inactive mode Jitter attenuation enable selected while reset is active (RST = 0) ...
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Table 6 Hardware Indication Signals Device Function Indicate LOS (loss of signal) Indicate BPV (bipolar violation) Data Sheet Functional Description Indication Signal LOS 0 = normal signal 1 = loss of signal BPV violation 1 = bipolar ...
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Interface Description 4.1 Receiver 4.1.1 Standard Receiver Application 75 Figure 7 Receiver Configuration Table 7 External Component Values for Receiver Parameter [nF ...
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Line Monitoring Application DSX cross connect point 75 R3 Figure 8 DS3 Line Monitoring Table 8 External Component Values for DS Line Monitoring Parameter ...
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Receive Line Interface The receive line interface consists of a pre-amplifier, a noise and crosstalk filter, a variable gain amplifier and an equalizer followed by the clock and data recovery. The noise and crosstalk filter reduces distortions within the ...
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Receive Clock and Data Recovery The receive clock and data recovery extracts the route clock RCLK from the digital data stream and converts the data stream into a dual rail bit stream. The clock and data recovery needs a ...
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HDB3 Code In the HDB3 line code each block of four consecutive zeros is replaced by either of two replacements codes which are B00V and 000V, where B represents a pulse which applies to the bipolar rule ("+1" or ...
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E3 LOS Definition Analog LOS is detected, if the signal level on pins RL1/2 drops below a fixed level ("B") for a certain period. Loss of signal level "B" is defined to be between 15 and 35 dB below ...
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Jitter Tolerance The TE3-LIU™ receiver’s tolerance to input jitter complies to and exceeds the relevant international standards. Especially the requirements of Telcordia GR-499-CORE (DS3), ITU-T G.824 (DS3), GR-253-CORE (STS-1) and ITU-T G.823 (E3) are fulfilled and exceeded. Figure 11 ...
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GR-499-CORE Cat. 1 Figure 12 Jitter Tolerance GR-499-CORE Jitter Tolerance Requirements (DS3) The input jitter tolerance is defined as the minimum amplitude of sinusodial jitter at a given frequency that when ...
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Transmitter The serial bit stream is then processed by the transmitter which has the following functions: • generation of AMI, B3ZS (DS3/STS-1) or HDB3 (E3) coded signals • all-ones generation (alarm indication signal) 4.2.1 Transmit Line Interface The received ...
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ANSI T1.102 (at cross connect point 450 ft.) are fulfilled. Note: An additional capacitor on the primary or secondary side of the transformer may be required in some applications to improve the pulse mask, if ...
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Jitter Attenuation Jitter is reduced in transmit direction, if the jitter attenuator is activated (JATT = 1). The JATT control signal enables/disables the jitter attenuation PLL and activates/bypasses the buffer. The jitter attenuator consists of a buffer and a ...
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Figure 15 Jitter Attenuation Characteristic 4.2.4 Intrinsic Jitter The TE3-LIU™ transmit PLL generates an output jitter which fulfills the requirements as specified in Table 14 below. Table 14 Transmit Output ...
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Pulse Shaper The internal pulse shaper generates the required pulse shapes for E3, DS3 and STS-1 signals according to ANSI T1.102, T1.404, Telcordia GR-499-CORE and ITU-T G.703). The specific pulse mask is fulfilled at the crossconnect point at a ...
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Although HDB3 coding is normally used with single rail NRZ data, the transmit line encoder accepts either dual rail or single rail data. Bipolar violations in an incoming dual rail data stream are converted to valid data pulses. 4.2.7 AIS ...
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Maintenance Functions 4.4.1 Remote Loop In the remote loopback mode the clock and data recovered from the line inputs RL1/2 are routed back to the line outputs XL1/ normal mode they are also processed by the synchronizer ...
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Local Loop The local loopback mode disconnects the receive lines RL1/2 from the receiver. Instead of the signals coming from the line data provided by system interface is routed through the analog receiver back to the framer interface. The ...
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Operational Description 5.1 Operational Overview The TE3-LIU™ can be operated in three principle modes, which are either E3, DS3 or STS-1 mode. This basic operation mode selection has to be stable before the reset signal goes inactive. The device ...
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Electrical Characteristics 6.1 Absolute Maximum Ratings Table 15 Maximum Ratings Parameter Ambient temperature under bias Storage temperature IC supply voltage (digital) IC supply voltage receive (analog) IC supply voltage transmit (analog) Voltage on any output pin with respect to ...
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Operating Range Table 16 Power Supply Range Parameter Ambient temperature Supply voltage Digital input voltages Ground Notes 1. In the operating range, the functions given in the circuit description are fulfilled. All V pins have to be connected to ...
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DC Characteristics Table 17 DC Parameters Parameter Input low voltage Input high voltage Output low voltage Output high voltage Average power supply current Input leakage current Input leakage current Input pullup current Input pulldown current Transmitter leakage current Transmitter ...
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Table 17 DC Parameters (cont’d) Parameter (cont’d) Receiver sensitivity Analog loss of Signal threshold E3 1) applies to all output pins except analog pins XL1/XL2 2) Input leakage currents of pins containing internal pullup devices are measured in a testmode ...
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AC Characteristics 6.4.1 Reset RES DS3/E3 DS3/STS-1 JATT (PLLs tuned) Figure 18 Reset Timing Table 18 Reset Timing Parameter Values No. Parameter 1 RES pulse width low 2 DS3/E3, DS3/STS-1, JATT to RES setup time 3 PLL startup time ...
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Reference Clock REFCLK Figure 19 Reference Clock Timing Table 19 REFCLK Timing Parameter Values No. Parameter 1 REFCLK period E3 REFCLK period DS3 REFCLK period STS-1 2 REFCLK high 3 REFCLK low 4 REFCLK rise time 5 REFCLK fall ...
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Jitter Attenuator Reference Clock XTAL1 Figure 20 XTAL Clock Timing • Table 20 XTAL Timing Parameter Values No. Parameter 1 XTAL1/2 period E3 XTAL1/2 period DS3 XTAL1/2 period STS-1 XTAL1 TE3-LIU TM XTAL2 Figure 21 Recommended Crystal Circuit Data ...
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Figure 22 Crystal Pulling Range Table 21 XTAL Crystal Parameter Values No. Parameter 1 Crystal nominal frequency DS3 Crystal nominal frequency STS-1 Crystal nominal ...
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Microprocessor Control CS Control Signal Figure 23 Chip Select Timing Table 22 Chip Select Timing Parameter Values No. Parameter 1 CS pulse width low 2 CS pulse width high 3 Control Signal Setup Time 4 Control Signal Hold Time ...
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Transmit Input Timing XCLK (XPE=0) XCLK (XPE=1) XDIP, XDIN Figure 24 XCLK Input Timing Table 23 XCLK Timing Parameter Values No. Parameter 1 XCLK period E3 XCLK period DS3 XCLK period STS-1 2 XCLK high 3 XCLK low 4 ...
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Receive Output Timing RCLK (RPE=0) RCLK (RPE=1) RDOP, RDON Figure 25 RCLK Output Timing Table 24 RCLK Timing Parameter Values No. Parameter 1 RCLK period E3 RCLK period DS3 RCLK period STS-1 2 RCLK high 3 RCLK low 4 ...
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Pulse Templates 6.4.7.1 Pulse Template E3 V 1.0 0.5 0 Figure 26 E3 Pulse Shape at Transmitter Output Table 25 E3 Pulse Mask No. Parameter Nominal peak voltage of a mark (pulse) Peak voltage of a space (no pulse) ...
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Pulse Template DS3 1.2 1.0 0.8 0.6 0.4 0.2 0 -0.2 -1.0 -0.5 Figure 27 DS3 Pulse Shape at the Cross Connect Point (450 ft.) Table 26 DS3 Pulse Mask (ANSI T1.404, GR-499-CORE) Absolute Voltage Level (100 % Value) ...
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Table 27 DS3 Pulse Mask (ANSI T1.404) Time T -0.36 -0.36 T +0.36 T +0.36 Time T -0.68 -0.68 T +0.36 T +0.36 Table 28 DS3 Pulse Mask (GR-499-CORE) Time -0.85 T -0.36 -0.36 T +0.36 +0.36 T Time -0.85 ...
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Pulse Template STS-1 1.2 1.0 0.8 0.6 0.4 0.2 0 -0.2 -1.0 -0.5 Figure 28 STS-1 Pulse Shape at the Cross Connect Point (450 ft.) Table 29 STS-1 Pulse Mask Min. - 2.7 dBm 1) bit sequence: (+1)0(-1)0(+1)0(-1)... Table ...
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Time -0.85 T -0.68 -0.68 T +0.26 +0.26 T Data Sheet Upper Curve 0.5 1 +1.4 62 PEF 3452 TE3-LIU V1.3 Electrical Characteristics Equation +0.03 T sin -- - 1 0. ---------- - + ...
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Capacitances Table 31 Pin Capacitances Parameter 1) Input capacitance 1) Output capacitance 1) Output capacitance 1) not tested in production 6.6 Package Characteristics Figure 29 Thermal Behavior of Package Table 32 Package Characteristic Values Parameter 1) Thermal Resistance Junction ...
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Test Configuration AC Test Level V T Drive Levels Figure 30 Input/Output Waveforms for AC Testing Table 33 AC Test Conditions Parameter Load Capacitance 1 Load Capacitance 2 Load Capacitance 3 Input Voltage high Input ...
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Package Outlines P-MQFP-44-2 (Plastic Metric Quad Flat Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Data Sheet 65 PEF 3452 TE3-LIU V1.3 Package Outlines ...
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Appendix 8.1 Cable Characteristics Cable characteristics are defined in ANSI T1.102 as shown below Figure 31 DS3 Cable Characteristics ...
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Application Example The following picture shows a typical application circuit (excluding surge protection). DS3/STS-1/E3 Receive Line Interface DS3/STS-1/E3 Transmit Line Interface Figure 32 Application Circuit Data Sheet Jitter Attenuation Reference C L XTAL1/2 VDDRP/VSSRP VDDR/VSSR RL1/2 Receive Path TM ...
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Index A AIS 20 Ambient temperature 53 AMI 35 ANSI 9, 72 Applications 12 B3ZS 35 buffer 44 C Cable 72 Clock 17, 19 Clock and Data Recovery crystal 44 Edge Selection 21 ESD 53 External ...
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W wander 38 X XCLK 62 XTAL 59 Data Sheet 69 PEF 3452 TE3-LIU V1.3 2005-01-24 ...
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... Published by Infineon Technologies AG ...