XC56309PV100A Freescale Semiconductor, XC56309PV100A Datasheet - Page 37

• Manufacturer Part Number: XC56309PV100A
• Manufacturer: Freescale Semiconductor

Specifications of XC56309PV100A

• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 102KB
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / Rohs Status: Not Compliant

Freescale Semiconductor
Notes:
No.
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
Page mode cycle time for two consecutive accesses of the same
direction
Page mode cycle time for mixed (read and write) accesses
CAS assertion to data valid (read)
Column address valid to data valid (read)
CAS deassertion to data not valid (read hold time)
Last CAS assertion to RAS deassertion
Previous CAS deassertion to RAS deassertion
CAS assertion pulse width
Last CAS deassertion to RAS assertion
•
•
•
CAS deassertion pulse width
Column address valid to CAS assertion
CAS assertion to column address not valid
Last column address valid to RAS deassertion
WR deassertion to CAS assertion
CAS deassertion to WR assertion
CAS assertion to WR deassertion
WR assertion pulse width
Last WR assertion to RAS deassertion
WR assertion to CAS deassertion
Data valid to CAS assertion (write)
CAS assertion to data not valid (write)
WR assertion to CAS assertion
Last RD assertion to RAS deassertion
RD assertion to data valid
RD deassertion to data not valid
WR assertion to data active
WR deassertion to data high impedance
1.
2.
3.
4.
5.
6.
BRW[1–0] = 00, 01—Not applicable
BRW[1–0] = 10
BRW[1–0] = 11
The number of wait states for Page mode access is specified in the DRAM Control Register.
The refresh period is specified in the DRAM Control Register.
The asynchronous delays specified in the expressions are valid for the DSP56309.
All the timings are calculated for the worst case. Some of the timings are better for specific cases (for example, t
listed, as appropriate.
BRW[1–0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of-page
access.
RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is t
T
C
for read-after-read or write-after-write sequences). An expressions is used to calculate the maximum or minimum value
Table 2-10.
Characteristics
6
5
DRAM Page Mode Timings, Four Wait States
DSP56309 Technical Data, Rev. 7
Symbol
t
t
t
t
t
t
t
t
t
RHCP
t
t
t
t
t
t
t
WCH
t
WCS
t
CAC
RSH
CRP
t
CAH
RCS
RCH
RWL
CWL
t
t
ROH
t
t
t
OFF
CAS
ASC
RAL
WP
PC
AA
CP
DS
DH
GA
GZ
1.25 × T
0.75 × T
Expression
2.75 × T
3.75 × T
5.25 × T
7.25 × T
1.25 × T
3.25 × T
3.75 × T
1.25 × T
3.25 × T
4.75 × T
0.5 × T
3.5 × T
2.5 × T
3.5 × T
4.5 × T
3.5 × T
4.5 × T
6 × T
2 × T
5 × T
0.25 × T
4.5 × T
T
5 × T
C
—
− 4.0
C
C
C
C
C
C
C
C
C
C
C
C
OFF
C
C
C
C
C
C
C
C
C
C
− 4.0
− 4.0
− 4.0
C
– 4.5
− 4.0
− 4.0
− 4.0
− 4.5
− 4.0
− 4.0
– 3.7
– 1.5
− 5.7
− 5.7
− 6.0
− 6.0
− 4.0
− 4.2
− 4.3
− 4.3
− 5.7
C
− 4.3
1,2,3
C
AC Electrical Characteristics
and not t
4
GZ
Min
50.0
45.0
31.0
56.0
21.0
46.5
66.5
16.0
31.0
46.0
28.3
40.5
43.2
33.2
31.0
41.0
0.0
6.0
8.5
8.8
0.5
8.2
0.0
6.0
—
—
—
—
—
.
100 MHz
PC
Max
21.8
31.8
26.8
2.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
equals 3 ×
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2-17
—