addition to the functions described in sections 3.1 and 3.2.
applied in normal operation, the test mode may be set thereby adversely affecting normal operation.
if cables for the related signals are routed in parallel, wiring noise larger than V
and RESET pins causing errors.
against noise using the following external components.
clock, the signal to be input or output to the P50 pin next to the XT2 pin must be a signal required to be switched
between high and low the minimum number of times (once or less per second).
of capacitance coupling of the P50 and XT2 pins and the correct watch functions cannot be achieved (the watch
P50 pin as shown below.
P00/INT4 and RESET pins have the function (especially for IC test) to test
The test mode is set when a voltage larger than V
Since there is a display output pin having a high-voltage amplitude (35 V) next to the P00/INT4 and RESET pins,
Thus, carry out wiring so that wiring noise can be minimized, If noise still cannot be suppressed, take the measure
When selecting the 32.768 kHz subsystem clock connected to the XT1 and XT2 pins as the watch timer source
If the P50 pin signal is switched frequently between high and low, a spike is generated in the XT2 pin because
If it is necessary to allow the P50 pin signal to switch between high and low, mount an external capacitor to the
Connect diode with small V
P00/INT4 PIN AND RESET PIN OPERATING PRECAUTIONS
XT1, XT2 AND P50 PIN OPERATING PRECAUTIONS
and P00/INT4, RESET
(0.3 V or less) between
is applied to one of these pins. If noise larger than V
Connect a capacitor between the pins and V
PD75216A internal operations in
may be applied to the P00/INT4