HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet
HD6417712BPV
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HD6417712BPV Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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SH7712 32 Hardware Manual Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series SH7712 HD6417712 Rev.1.00 2005.12 ...
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Rev. 1.00 Dec. 27, 2005 Page ii of xlii ...
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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...
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General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test ...
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Rev. 1.00 Dec. 27, 2005 Page v of xlii ...
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Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules • On-Chip ...
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Rev. 1.00 Dec. 27, 2005 Page vii of xlii ...
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The SH7712 RISC (Reduced Instruction Set Computer) microcomputer includes a Renesas Technology original RISC CPU as its core, and the peripheral functions required to configure a system. Target Users: This manual was written for users who will be using this ...
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Rules: Register name: Bit order: Number notation: Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx. Signal notation: Related Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions ...
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Abbreviations ACIA Asynchronous communication interface adapter AUD Advanced user debugger BSC Bus state controller CPG Clock pulse generator DMA Direct memory access DMAC Direct memory access controller etu Elementary time unit FIFO First-in first-out H-UDI User debugging interface INTC Interrupt ...
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Rev. 1.00 Dec. 27, 2005 Page xi of xlii ...
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Section 1 Overview and Pin Function ................................................................... 1 1.1 Features.................................................................................................................................. 1 1.2 Block Diagram....................................................................................................................... 7 1.3 Pin Description ...................................................................................................................... 8 1.3.1 Pin Assignment......................................................................................................... 8 1.3.2 Pin Functions .......................................................................................................... 19 Section 2 CPU ..................................................................................................... 27 2.1 Processing States and Processing Modes............................................................................. ...
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DSP Registers ......................................................................................................... 77 3.3 CPU Extended Instructions.................................................................................................. 78 3.3.1 Repeat Control Instructions .................................................................................... 78 3.3.2 Extended Repeat Control Instructions .................................................................... 88 3.4 DSP Data Transfer Instructions ........................................................................................... 93 3.4.1 General Registers.................................................................................................... 97 3.4.2 DSP Data Addressing ............................................................................................. 99 ...
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Exception Vector Addresses................................................................................. 160 4.2.3 Exception Codes ................................................................................................... 160 4.2.4 Exception Request and BL Bit (Multiple Exception Prevention) ......................... 160 4.2.5 Exception Source Acceptance Timing and Priority .............................................. 161 4.3 Individual Exception Operations ....................................................................................... 165 4.3.1 Resets.................................................................................................................... 165 4.3.2 ...
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Data Array ............................................................................................................ 211 5.6.3 Usage Examples.................................................................................................... 213 5.7 Usage Note......................................................................................................................... 213 Section 6 Cache .................................................................................................215 6.1 Features.............................................................................................................................. 215 6.1.1 Cache Structure..................................................................................................... 215 6.2 Register Descriptions ......................................................................................................... 217 6.2.1 Cache Control Register 1 (CCR1) ........................................................................ 217 6.2.2 Cache Control ...
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Interrupt Sources................................................................................................................ 237 8.3.1 NMI Interrupt........................................................................................................ 237 8.3.2 IRQ Interrupts....................................................................................................... 238 8.3.3 IRL Interrupts ....................................................................................................... 238 8.3.4 On-Chip Peripheral Module Interrupts ................................................................. 239 8.3.5 Interrupt Exception Handling and Priority............................................................ 240 8.4 Register Descriptions......................................................................................................... 246 8.4.1 Interrupt Priority Registers A ...
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Flow of the User Break Operation ........................................................................ 281 9.3.2 Break on Instruction Fetch Cycle.......................................................................... 283 9.3.3 Break on Data Access Cycle................................................................................. 283 9.3.4 Break on X/Y-Memory Bus Cycle........................................................................ 285 9.3.5 Sequential Break ................................................................................................... 285 9.3.6 Value of Saved Program ...
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Watchdog Timer Counter (WTCNT).................................................................... 324 11.7.2 Watchdog Timer Control/Status Register (WTCSR)............................................ 324 11.7.3 Notes on Register Access ..................................................................................... 326 11.8 Using WDT........................................................................................................................ 327 11.8.1 Canceling Standbys .............................................................................................. 327 11.8.2 Changing Frequency ............................................................................................. 328 11.8.3 Using Watchdog Timer Mode .............................................................................. ...
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Section 13 Direct Memory Access Controller (DMAC) ...................................459 13.1 Features.............................................................................................................................. 459 13.2 Input/Output Pins ............................................................................................................... 461 13.3 Register Descriptions ......................................................................................................... 462 13.3.1 DMA Source Address Register (SAR) ................................................................. 463 13.3.2 DMA Destination Address Register (DAR) ......................................................... 463 13.3.3 DMA Transfer ...
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Counter (R64CNT) .................................................................................... 508 15.3.2 Second Counter (RSECCNT) ............................................................................... 508 15.3.3 Minute Counter (RMINCNT)............................................................................... 509 15.3.4 Hour Counter (RHRCNT) .................................................................................... 509 15.3.5 Day of Week Counter (RWKCNT) ...................................................................... 510 15.3.6 Date Counter (RDAYCNT) .................................................................................. 512 15.3.7 Month Counter ...
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Serial Status Register (SCFSR) ............................................................................ 545 16.3.8 Bit Rate Register (SCBRR) .................................................................................. 553 16.3.9 FIFO Control Register (SCFCR) .......................................................................... 554 16.3.10 FIFO Data Count Register (SCFDR) .................................................................... 556 16.3.11 Line Status Register (SCLSR) .............................................................................. 558 16.4 Operation ........................................................................................................................... 559 ...
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Usage Notes ....................................................................................................................... 635 Section 18 Ethernet Controller (EtherC) ........................................................... 637 18.1 Features.............................................................................................................................. 637 18.2 Input/Output Pins............................................................................................................... 639 18.3 Register Descriptions......................................................................................................... 641 18.3.1 Software Reset Register (ARSTR) ....................................................................... 644 18.3.2 EtherC Mode Register (ECMR)............................................................................ 645 18.3.3 EtherC Status Register ...
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Relay Status Interrupt Mask Register (TSU_FWINMK)...................................... 675 18.3.36 Added Qtag Value Set Register (Port (TSU_ADQT0).............................. 679 18.3.37 Added Qtag Value Set Register (Port (TSU_ADQT1).............................. 680 18.3.38 CAM Entry Table Busy Register (TSU_ADSBSY) ............................................. ...
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MII Frame Timing ................................................................................................ 717 18.4.6 Accessing MII Registers....................................................................................... 719 18.4.7 Magic Packet Detection ........................................................................................ 722 18.4.8 Operation by IPG Setting...................................................................................... 723 18.4.9 Direction for IEEE802.1Q Qtag ........................................................................... 723 18.5 Connection to LSI.............................................................................................................. 725 Section 19 Ethernet Controller Direct ...
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Section 20 Pin Function Controller (PFC).........................................................779 20.1 Overview............................................................................................................................ 779 20.2 Register Configuration....................................................................................................... 780 20.3 Register Descriptions ......................................................................................................... 781 20.3.1 Port A Control Register (PACR) .......................................................................... 781 20.3.2 Port B Control Register (PBCR)........................................................................... 782 20.3.3 Port C Control Register (PCCR)........................................................................... 783 ...
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Register States in Each Operating Mode ........................................................................... 845 Section 24 Electrical Characteristics ................................................................. 855 24.1 Absolute Maximum Ratings .............................................................................................. 855 24.2 DC Characteristics ............................................................................................................. 857 24.3 AC Characteristics ............................................................................................................. 859 24.3.1 Clock Timing ........................................................................................................ 860 24.3.2 Control Signal Timing ...
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Section 1 Overview Figure 1.1 Block Diagram .............................................................................................................. 7 Figure 1.2 Pin Assignment (HQFP2828-256(FP-256G/GV)) ........................................................ 8 Figure 1.3 Pin Assignment (P-LFBGA1717-256(BP-256H/HV)).................................................. 9 Section 2 CPU Figure 2.1 Processing State Transitions........................................................................................ 28 Figure 2.2 Logical Address to External Memory Space Mapping................................................ ...
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Section 4 Exception Handling Figure 4.1 Register Bit Configuration ........................................................................................ 156 Section 5 Memory Management Unit (MMU) Figure 5.1 MMU Functions ........................................................................................................ 183 Figure 5.2 Virtual Address Space (MMUCR.AT = 1)................................................................ 185 Figure 5.3 Virtual Address Space (MMUCR.AT = 0)................................................................ ...
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Figure 10.6 STATUS Output when Software Standby Mode is Canceled by Manual Reset ..... 308 Figure 10.7 STATUS Output when Sleep Mode is Canceled by Interrupt................................. 309 Figure 10.8 STATUS Output when Sleep Mode is Canceled by Power-on Reset...................... 309 ...
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Figure 12.26 Self-Refresh Timing .............................................................................................. 432 Figure 12.27 Access Timing in Low-Frequency Mode .............................................................. 433 Figure 12.28 Access Timing in Power-Down Mode .................................................................. 434 Figure 12.29 Write Timing for SDRAM Mode Register (Based on JEDEC)............................. 437 Figure 12.30 EMRS Command ...
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Figure 13.9 DMA Transfer Example in Cycle-Steal Mode (Dual Address, DREQ Low Level Detection)......................................................... 487 Figure 13.10 DMA Transfer Example in Burst Mode (Dual Address, DREQ Low Level Detection)....................................................... 487 Figure 13.11 Bus State when Multiple Channels are Operating ................................................. ...
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Figure 16.10 RTS Control Operation ......................................................................................... 572 Figure 16.11 Data Format in Clock Synchronous Communication............................................ 572 Figure 16.12 Sample the SCIF Initialization Flowchart ............................................................. 574 Figure 16.13 Sample Serial Transmission Flowchart ................................................................. 575 Figure 16.14 Example of the SCIF Transmit ...
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Figure 18.7 (2) MII Frame Transmit Timing (Collision)............................................................ 717 Figure 18.7 (3) MII Frame Transmit Timing (Transmit Error)................................................... 718 Figure 18.7 (4) MII Frame Receive Timing (Normal Reception)............................................... 718 Figure 18.7 (5) MII Frame Receive Timing (Reception Error (1))............................................. 718 ...
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Figure 24.8 Oscillation Settling Time at Standby Return (Return by IRQ5 to IRQ0 and IRL3 to IRL0)......................................................... 863 Figure 24.9 PLL Synchronization Settling Time by Reset or NMI ............................................ 863 Figure 24.10 PLL Synchronization Settling Time by IRQ/IRL Interrupts ................................. ...
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Figure 24.32 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4) (Bank Active Mode, PRE + ACTV + READ Commands, Different Row Address, CAS Latency = 2, TRCD = 1 Cycle)............................................. 885 Figure 24.33 Synchronous DRAM Burst Write Bus ...
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Figure 24.59 MII Transmit Timing (Normal Operation)............................................................ 909 Figure 24.60 MII Transmit Timing (Case of Conflict)............................................................... 909 Figure 24.61 MII Receive Timing (Normal Operation) ............................................................. 910 Figure 24.62 MII Receive Timing (Case of Error) ..................................................................... 910 Figure 24.63 MDIO Input ...
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Section 1 Overview Table 1.1 Pin Assigument ....................................................................................................... 10 Table 1.2 Pin Functions .......................................................................................................... 19 Section 2 CPU Table 2.1 Logical Address Space............................................................................................ 30 Table 2.2 Register Initial Values............................................................................................. 33 Table 2.3 Addressing Modes and Effective Addresses for CPU Instructions......................... ...
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Table 3.20 Examples of NOPX and NOPY Instruction Codes............................................... 116 Table 3.21 Variation of ALU Fixed-Point Operations............................................................ 119 Table 3.22 Correspondence between Operands and Registers ............................................... 119 Table 3.23 Variation of ALU Integer Operations ................................................................... 124 Table 3.24 Variation of ...
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Section 7 X/Y Memory Table 7.1 X/Y Memory Logical Addresses .......................................................................... 231 Table 7.2 MMU and Cache Settings..................................................................................... 234 Section 8 Interrupt Controller (INTC) Table 8.1 Pin Configuration.................................................................................................. 237 Table 8.2 Interrupt Exception Handling Sources and Priority (IRQ Mode) ......................... ...
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Table 12.13 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (2)-1 ........................................................................... 405 Table 12.13 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (2)-2 ........................................................................... 406 Table 12.14 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (3)............................................................................... ...
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Table 16.2 Relationship between n and Clock........................................................................ 553 Table 16.3 SCSMR Settings for Serial Transfer Format Selection......................................... 560 Table 16.4 SCSMR and SCSCR Settings for the SCIF Clock Source Selection .................... 560 Table 16.5 Serial Transfer Formats......................................................................................... 562 Table 16.6 ...
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Section 24 Electrical Characteristics Table 24.1 Absolute Maximum Ratings ................................................................................. 855 Table 24.2 DC Characteristics (1) .......................................................................................... 857 Table 24.2 DC Characteristics (2) .......................................................................................... 858 Table 24.3 Permitted Output Current Values.......................................................................... 859 Table 24.4 Maximum Operating Frequencies......................................................................... 859 Table 24.5 ...
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Section 1 Overview and Pin Function This LSI is a 32-bit reduced instruction set computer (RISC) microprocessor that is built on the SuperH architecture. Its core is a RISC-type CPU with a Digital Signal Processor (DSP functional extension. ...
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Section 1 Overview and Pin Function • Space identifier ASID: 8 bits, 256 logical address spaces • Supports five-stage pipeline DSP: • Mixture of 16-bit and 32-bit instructions • 32-/40-bit internal data bus • Multiplier, ALU, and barrel shifter • ...
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Cache memory: • 32-kbyte cache, mixture of instructions and data • 512-entry, 4-way set associative, 16-byte block length • Write-back, write-through, LRU replacement algorithm • 1-stage write-back buffer X/Y memory: • Three independent read/write ports 8-/16-/32-bit access from the CPU ...
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Section 1 Overview and Pin Function • Supports power-down modes: Sleep mode Software standby mode Module standby mode • A single channel on-chip watch dog timer Watchdog timer mode and interval timer mode is selectable. An interrupt can be generated ...
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Serial communication interface with FIFO (SCIF): • 16 bytes each for transmit/receive FIFO • Two channels (SCIF0 and SCIF1) • CTS/RTS (flow control) support • Asynchronous and synchronous modes • Full-duplex communication support • DMA transfer Serial I/O with FIFO ...
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Section 1 Overview and Pin Function • Transfer data width: 32 bits • Address space: 4 Gbytes • On-chip FIFO (2-kbytes each for transmit/receive) User debugging interface (H-UDI): • Supports the E10A emulator • Realtime branch trace • 1-kbyte of ...
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Block Diagram SuperH DSP core CPU core X/Y memory Instructions/data for CPU/DSP 16 kbytes Bus state Peripheral controller bus (BSC) controller External bus Serial Serial I/O communication 128-byte with FIFO interface SRAM with FIFO (SIOF)* (SCIF)* Note: * SCIF ...
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Section 1 Overview and Pin Function 1.3 Pin Description 1.3.1 Pin Assignment 193 VccQ-RTC(3.3V) 194 XTAL2 EXTAL2 195 VssQ-RTC(0V) 196 ASEMD0 197 198 TDI 199 TMS TDO 200 TRST 201 202 TCK ASEBRKAK 203 AUDSYNC 204 AUDCK 205 Vcc(1.5V) 206 ...
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INDEX CS5B/ PTC6/ A PTC4/ EXTAL MD3 MD1 CE1A CE2B SIOFSYNC1 REFOUT/ B IRQOUT/ VssQ XTAL MD2 VssQ Vss-PLL1 ARBUSY PTC7/ C CS4 BREQ Vcc-PLL1Vss-PLL2 Vcc-PLL2 IOIS16 CS6B/ D CS6A CS5A VccQ MD0 VccQ CE1B ...
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Section 1 Overview and Pin Function Table 1.1 Pin Assigument Pin No. Pin No Pin Name FP-256G/GV) (BP-256H/HV REFOUT/IRQOUT ARBUSY BREQ VccQ 4 B1 VssQ BACK 5 E2 CS0 6 E3 CS4 ...
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Pin No. Pin No Pin Name FP-256G/GV) (BP-256H/ D11 31 K1 D12 32 L1 D13 33 L4 D14 34 M1 D15 35 L3 Vcc 36 L2 Vss WE0(BE0)/DQMLL 37 M4 WE1(BE1)/DQMLU ...
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Section 1 Overview and Pin Function Pin No. Pin No Pin Name FP-256G/GV) (BP-256H/ A10 63 V2 A11 64 Y1 A12 65 W2 A13 66 W3 A14 67 W4 A15 ...
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Pin No. Pin No Pin Name FP-256G/GV) (BP-256H/ D27 90 U9 D28 91 Y9 D29 92 V10 VccQ 93 W10 VssQ 94 U10 D30 95 Y10 D31 96 Y11 A18 97 U11 A19 98 Y12 A20 ...
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Section 1 Overview and Pin Function Pin No. Pin No Pin Name FP-256G/GV) (BP-256H/HV 120 Y18 PTA2/SCIF0CK 121 W17 VccQ 122 Y19 VssQ 123 V18 PTA3/SCK_SIO0 124 W16 PTA4/SIOMCLK0 125 V16 PTA5/RXD_SIO0 126 V17 PTA6/TXD_SIO0 127 W18 PTA7/SIOFSYNC0 ...
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Pin No. Pin No Pin Name FP-256G/GV) (BP-256H/HV 150 N17 ERXD13 151 N20 MDC1 152 M18 MDIO1 153 M19 WOL1 154 M17 LNKSTA1 155 M20 EXOUT1/TEND1 156 L18 CAMSEN1/IRQ5 157 L19 CRS0 158 L17 Vcc 159 L20 Vss ...
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Section 1 Overview and Pin Function Pin No. Pin No Pin Name FP-256G/GV) (BP-256H/HV 179 F18 MDC0 180 D20 MDIO0 181 E17 WOL0 182 F19 LNKSTA0 183 D17 EXOUT0/TEND0 184 C20 CAMSEN0/IRQ4 185 D19 VccQ 186 B20 VssQ ...
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Pin No. Pin No Pin Name FP-256G/GV) (BP-256H/HV 208 C14 VccQ 209 A15 VssQ 210 D14 AUDATA3 211 B13 AUDATA2 212 C13 AUDATA1 213 A14 AUDATA0 RESETM 214 D13 RESETP 215 A13 216 C12 NMI 217 B12 IRQ0/IRL0 ...
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Section 1 Overview and Pin Function Pin No. Pin No Pin Name FP-256G/GV) (BP-256H/HV 239 C7 PTC5/CE2A 240 A5 PTC6/CE2B 241 D6 VccQ 242 B7 VssQ 243 C6 PTC7/IOIS16 CS5B/CE1A 244 A4 CS6B/CE1B 245 D5 246 B6 VssQ ...
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Pin Functions Table 1.2 lists the pin functions. Table 1.2 Pin Functions Classification Symbol Power supply Vcc Vss VccQ VssQ Clock Vcc-PLL1 Vss-PLL1 Vcc-PLL2 Vss-PLL2 EXTAL Section 1 Overview and Pin Function I/O Name Function Power supply Power ...
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Section 1 Overview and Pin Function Classification Symbol Clock XTAL CKIO CKIO2 Operating mode MD5 to MD0 control RESETP System control RESETM STATUS1 STATUS0 BREQ BACK Rev. 1.00 Dec. 27, 2005 Page 20 of 932 REJ09B0269-0100 I/O Name Function O ...
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Classification Symbol Interrupts NMI IRQ5 to IRQ0 IRL3 to IRL0 IRQOUT Address bus A25 to A0 Data bus D31 to D0 CS0, Bus control CS2 to CS4, CS5A, CS6A, CS5B/CE1A, CS6B/CE1B, CE2A, CE2B RD RD/WR BS WE3(BE3)/ ICIOWR WE2(BE2)/ ICIORD ...
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Section 1 Overview and Pin Function Classification Symbol WE0(BE0) Bus control RAS CAS CKE IOIS16 DQMUU DQMUL DQMLU DQMLL REFOUT WAIT Direct memory DREQ0, access controller DREQ1 (DMAC) DACK0, DACK1 TEND0, TEND1 Rev. 1.00 Dec. 27, 2005 Page 22 of ...
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Classification Symbol User debugging TCK interface (H-UDI) TMS TDI TDO TRST Advanced user AUDATA3 to debugger (AUD) AUDATA0 AUDCK AUDSYNC ASEBRKAK E10A interface ASEMD0 Realtime clock VccQ-RTC (RTC) VssQ-RTC EXTAL2 XTAL2 Section 1 Overview and Pin Function I/O Name Function ...
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Section 1 Overview and Pin Function Classification Symbol Ethernet CRS1, controller CRS0 (EtherC1/0) COL1, COL0 ETXD13 to ETXD10 ETXD03 to ETXD00 TX-EN1, TX-EN0 TX-CLK1, TX-CLK0 TX-ER1, TX-ER0 RX-ER1, RX-ER0 Rev. 1.00 Dec. 27, 2005 Page 24 of 932 REJ09B0269-0100 I/O ...
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Classification Symbol Ethernet RX-CLK1, controller RX-CLK0 (EtherC1/0) RX-DV1, RX-DV0 ERXD13 to ERXD10 ERXD03 to ERXD00 MDC1, MDC0 MDIO1, MDIO0 WOL1, WOL0 LNKSTA1, LNKSTA0 EXOUT1, EXOUT0 CAMSEN1, CAMSEN0 Section 1 Overview and Pin Function I/O Name Function I MAC1/0 receive Timing ...
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Section 1 Overview and Pin Function Classification Symbol ARBUSY Ethernet controller (EtherC1/0) CTS1, Serial CTS0 communication interface with FIFO (SCIF1/0) RTS1, RTS0 RXD1, RXD0 TXD1, TXD0 SCIF1CK, SCIF0CK Serial I/O with SCK_SIO1, FIFO (SIOF1/0) SCK_SIO0 SIOMCLK1, SIOMCLK 0 RXD_SIO1, RXD_SIO0 ...
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Processing States and Processing Modes 2.1.1 Processing States This LSI supports four types of processing states: a reset state, an exception handling state, a program execution state, and a low-power consumption state, according to the CPU processing states. Reset ...
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Section 2 CPU 2.1.2 Processing Modes This LSI supports two processing modes: user mode and privileged mode. These processing modes can be determined by the processing mode bit (MD) of the status register (SR). If the MD bit is cleared ...
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Memory Map 2.2.1 Logical Address Space The LSI supports 32-bit logical addresses and accesses system resources using the 4-Gbytes of logical address space. User programs and data are accessed from the logical address space. The logical address space is ...
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Section 2 CPU Table 2.1 Logical Address Space Address Range Name Mode H'00000000 to P0/U0 Privileged/user mode H'7FFFFFFF H'80000000 to P1 Privileged mode H'9FFFFFFF H'A0000000 to P2 Privileged mode H'BFFFFFFF H'C0000000 to P3 Privileged mode H'DFFFFFFF H'E0000000 to P4 Privileged ...
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H'0000 0000 P0 area H'8000 0000 P1 area H'A000 0000 P2 area H'C000 0000 P3 area H'E000 0000 P4 area H'FFFF FFFF Privileged mode Figure 2.2 Logical Address to External Memory Space Mapping External memory space Area 0 Area 1 ...
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Section 2 CPU 2.3 Register Descriptions This LSI provides thirty-three 32-bit registers: 24 general registers, five control registers, three system registers, and one program counter. General Registers: This LSI incorporates 24 general registers: R0_BANK0 to R7_BANK0, R0_BANK1 to R7_BANK1 and ...
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Table 2.2 Register Initial Values Register Type Registers General registers R0_BANK0 to R7_BANK0, R0_BANK1 to R7_BANK1 R15 System registers MACH, MACL, PR Program counter PC Control registers SR GBR, SSR, SPC VBR Note: Initialized by a power-on or ...
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Section 2 CPU 31 *1,*2 R0_BANK0 *2 R1_BANK0 *2 R2_BANK0 *2 R3_BANK0 *2 R4_BANK0 *2 R5_BANK0 *2 R6_BANK0 *2 R7_BANK0 R8 R9 R10 R11 R12 R13 R14 R15 SR GBR MACH MACL PR PC (a) User mode register configuration Notes: ...
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General Registers There are twenty-four 32-bit general registers: R0_BANK0 to R7_BANK0, R0_BANK1 to R7_BANK1, and R8 to R15 are banked. The process mode and the register bank (RB) bit in the status register (SR) define which ...
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Section 2 CPU 31 *1,* R10 R11 R12 R13 R14 R15 2.3.2 System Registers The system registers: multiply and accumulate registers (MACH/MACL) and ...
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Program Counter The program counter (PC) stores the value obtained by adding 4 to the current instruction address. There is no instruction to read the PC directly. Before an exception handling state is entered, the PC is saved in ...
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Section 2 CPU 2.3.4 Control Registers The control registers (SR, GBR, SSR, SPC, and VBR) can be accessed by the LDC or STC instruction in privileged mode. The GBR register can be accessed in the user mode. The control registers ...
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Initial Bit Bit Name Value All 0 10 All 1 All 0 R/W Description R/W Block ...
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Section 2 CPU Initial Bit Bit Name Value Note: The and T bits can be set/cleared by the user mode specific instructions. Other bits can be read or written in privileged mode. Save Status ...
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Save status register (SSR SSR Save program counter (SPC SPC Global base register (GBR GBR Vector base register (VBR VBR Status register (SR Figure 2.6 Control ...
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Section 2 CPU 2.4 Data Formats 2.4.1 Register Data Format Register operands are always longwords (32 bits). When the memory operand is only a byte (8 bits word (16 bits sign-extended into a longword when loaded ...
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Byte position in R0 Byte position [7:0] in memory @(R1+0) @(R1+1) @(R1+2) @(R1+3) (a) Byte access Example: MOV.B R0, @R1 (R1 = Address 4n) Figure 2.7 Data Format on Memory (Big Endian Mode) The little endian mode ...
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Section 2 CPU Note: When the external memory is accessed through the E-DMAC module, big endian is supported, but little endian is not supported. Therefore, if the external memory is accessed through the E-DMAC module in little endian mode, data ...
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Literal Constant: Byte literal constant is placed inside the instruction code as immediate data. Since the instruction length is fixed to 16 bits, word and longword literal constant is not placed inside the instruction code, but in a table in ...
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Section 2 CPU Addressing Instruction Mode Format Register @–Rn indirect with pre-decrement Register @(disp:4, indirect with Rn) displacement Indexed @(R0, Rn) register indirect GBR indirect @(disp:8, with GBR) displacement Rev. 1.00 Dec. 27, 2005 Page 46 of 932 REJ09B0269-0100 Effective ...
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Addressing Instruction Mode Format Indexed GBR @(R0, indirect GBR) PC-relative with @(disp:8, displacement PC) PC-relative disp:8 disp:12 Effective Address Calculation Method Effective address is sum of register GBR and R0 contents. GBR + GBR + R0 R0 Effective address is ...
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Section 2 CPU Addressing Instruction Mode Format PC-relative Rn Immediate #imm:8 #imm:8 #imm:8 Note: For addressing modes with displacement (disp) as shown below, the assembler description in this manual indicates the value before it is scaled (x 1, x2, or ...
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Table 2.4 CPU Instruction Formats Instruction Format 0 type 15 0 xxxx xxxx xxxx xxxx n type 15 0 xxxx nnnn xxxx xxxx m type 15 0 xxxx xxxx xxxx mmmm nm type 15 0 xxxx nnnn xxxx mmmm Source ...
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Section 2 CPU Instruction Format nm type md type 15 0 xxxx xxxx dddd mmmm nd4 type 15 0 xxxx xxxx nnnn dddd nmd type 15 0 xxxx nnnn dddd mmmm d type 15 0 xxxx xxxx dddd dddd d12 ...
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Instruction Format i type 15 0 xxxx xxxx type 15 0 xxxx nnnn Note: In multiply-and-accumulate instructions, nnnn is the source register. * ...
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Section 2 CPU 2.6 Instruction Set 2.6.1 CPU Instruction Set Based on Functions The CPU instruction set consists of 68 basic instruction types divided into six functional groups, as shown in table 2.5. Tables 2.6 to 2.11 show the instruction ...
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Kinds of Type Instruction Arithmetic 21 operation instructions Logic 6 operation instructions Shift 12 instructions Op Code Function MAC Multiply-and-accumulate, double- precision multiply-and-accumulate MUL Double-precision multiplication (32 × 32 bits) Signed multiplication (16 × 16 bits) MULS Unsigned multiplication (16 ...
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Section 2 CPU Kinds of Type Instruction Branch 9 instructions System 15 control instructions Total: 68 The instruction code, operation, and number of execution states of the CPU instructions are shown in the following tables, classified by instruction type, using ...
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Instruction Instruction Code Indicated in MSB ↔ Indicated by mnemonic. LSB order. Explanation of Symbols Explanation of Symbols OP.Sz SRC, DEST mmmm: Source register OP: Operation code nnnn: Destination register Sz: Size 0000: R0 SRC: Source 0001: R1 DEST: Destination ...
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Section 2 CPU Table 2.6 Data Transfer Instructions Instruction Instruction Code MOV #imm,Rn 1110nnnniiiiiiii MOV.W @(disp,PC),Rn 1001nnnndddddddd MOV.L @(disp,PC),Rn 1101nnnndddddddd MOV Rm,Rn 0110nnnnmmmm0011 MOV.B Rm,@Rn 0010nnnnmmmm0000 MOV.W Rm,@Rn 0010nnnnmmmm0001 MOV.L Rm,@Rn 0010nnnnmmmm0010 MOV.B @Rm,Rn 0110nnnnmmmm0000 MOV.W @Rm,Rn 0110nnnnmmmm0001 MOV.L @Rm,Rn ...
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Instruction Instruction Code MOV.B @(R0,Rm),Rn 0000nnnnmmmm1100 MOV.W @(R0,Rm),Rn 0000nnnnmmmm1101 MOV.L @(R0,Rm),Rn 0000nnnnmmmm1110 MOV.B R0,@(disp,GBR) 11000000dddddddd MOV.W R0,@(disp,GBR) 11000001dddddddd MOV.L R0,@(disp,GBR) 11000010dddddddd MOV.B @(disp,GBR),R0 11000100dddddddd MOV.W @(disp,GBR),R0 11000101dddddddd MOV.L @(disp,GBR),R0 11000110dddddddd MOVA @(disp,PC),R0 11000111dddddddd MOVT Rn 0000nnnn00101001 SWAP.B Rm,Rn 0110nnnnmmmm1000 SWAP.W ...
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Section 2 CPU Table 2.7 Arithmetic Operation Instructions Instruction Instruction Code ADD Rm,Rn 0011nnnnmmmm1100 ADD #imm,Rn 0111nnnniiiiiiii ADDC Rm,Rn 0011nnnnmmmm1110 ADDV Rm,Rn 0011nnnnmmmm1111 CMP/EQ #imm,R0 10001000iiiiiiii CMP/EQ Rm,Rn 0011nnnnmmmm0000 CMP/HS Rm,Rn 0011nnnnmmmm0010 CMP/GE Rm,Rn 0011nnnnmmmm0011 CMP/HI Rm,Rn 0011nnnnmmmm0110 CMP/GT Rm,Rn ...
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Instruction Instruction Code DT Rn 0100nnnn00010000 EXTS.B Rm,Rn 0110nnnnmmmm1110 EXTS.W Rm,Rn 0110nnnnmmmm1111 EXTU.B Rm,Rn 0110nnnnmmmm1100 EXTU.W Rm,Rn 0110nnnnmmmm1101 MAC.L @Rm+, 0000nnnnmmmm1111 @Rn+ MAC.W @Rm+, 0100nnnnmmmm1111 @Rn+ MUL.L Rm,Rn 0000nnnnmmmm0111 MULS.W Rm,Rn 0010nnnnmmmm1111 MULU.W Rm,Rn 0010nnnnmmmm1110 NEG Rm,Rn 0110nnnnmmmm1011 NEGC Rm,Rn ...
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Section 2 CPU Table 2.8 Logic Operation Instructions Instruction Instruction Code AND Rm,Rn 0010nnnnmmmm1001 AND #imm,R0 11001001iiiiiiii AND.B #imm,@(R0, 11001101iiiiiiii GBR) NOT Rm,Rn 0110nnnnmmmm0111 OR Rm,Rn 0010nnnnmmmm1011 OR #imm,R0 11001011iiiiiiii OR.B #imm,@(R0, 11001111iiiiiiii GBR) TAS.B @Rn 0100nnnn00011011 TST Rm,Rn 0010nnnnmmmm1000 ...
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Table 2.9 Shift Instructions Instruction Instruction Code ROTL Rn 0100nnnn00000100 ROTR Rn 0100nnnn00000101 ROTCL Rn 0100nnnn00100100 ROTCR Rn 0100nnnn00100101 SHAD Rm, Rn 0100nnnnmmmm1100 SHAL Rn 0100nnnn00100000 SHAR Rn 0100nnnn00100001 SHLD Rm, Rn 0100nnnnmmmm1101 SHLL Rn 0100nnnn00000000 SHLR Rn 0100nnnn00000001 SHLL2 ...
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Section 2 CPU Table 2.10 Branch Instructions Instruction Instruction Code BF label 10001011dddddddd BF/S label 10001111dddddddd BT label 10001001dddddddd BT/S label 10001101dddddddd BRA label 1010dddddddddddd BRAF Rm 0000mmmm00100011 BSR label 1011dddddddddddd BSRF Rm 0000mmmm00000011 JMP @Rm 0100mmmm00101011 JSR @Rm 0100mmmm00001011 ...
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Table 2.11 System Control Instructions Instruction Instruction Code CLRMAC 0000000000101000 CLRS 0000000001001000 CLRT 0000000000001000 LDC Rm,SR 0100mmmm00001110 LDC Rm,GBR 0100mmmm00011110 LDC Rm,VBR 0100mmmm00101110 LDC Rm,SSR 0100mmmm00111110 LDC Rm,SPC 0100mmmm01001110 LDC Rm,R0_BANK 0100mmmm10001110 LDC Rm,R1_BANK 0100mmmm10011110 LDC Rm,R2_BANK 0100mmmm10101110 LDC Rm,R3_BANK ...
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Section 2 CPU Instruction Instruction Code LDC.L @Rm+, 0100mmmm11000111 R4_BANK LDC.L @Rm+, 0100mmmm11010111 R5_BANK LDC.L @Rm+, 0100mmmm11100111 R6_BANK LDC.L @Rm+, 0100mmmm11110111 R7_BANK LDS Rm,MACH 0100mmmm00001010 LDS Rm,MACL 0100mmmm00011010 LDS Rm,PR 0100mmmm00101010 LDS.L @Rm+,MACH 0100mmmm00000110 LDS.L @Rm+,MACL 0100mmmm00010110 LDS.L @Rm+,PR 0100mmmm00100110 ...
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Instruction Instruction Code STC R5_BANK,Rn 0000nnnn11010010 STC R6_BANK,Rn 0000nnnn11100010 STC R7_BANK,Rn 0000nnnn11110010 STC.L SR,@–Rn 0100nnnn00000011 STC.L GBR,@–Rn 0100nnnn00010011 STC.L VBR,@–Rn 0100nnnn00100011 STC.L SSR,@–Rn 0100nnnn00110011 STC.L SPC,@–Rn 0100nnnn01000011 STC.L R0_BANK,@– 0100nnnn10000011 Rn STC.L R1_BANK,@– 0100nnnn10010011 Rn STC.L R2_BANK,@– 0100nnnn10100011 Rn STC.L ...
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Section 2 CPU 2.6.2 Operation Code Map Table 2.12 shows the operation code map. Table 2.12 Operation Code Map Instruction Code Fx: 0000 MSB LSB MD: 00 0000 Rn Fx 0000 0000 Rn Fx 0001 0000 Rn 00MD 0010 STC ...
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Instruction Code Fx: 0000 MSB LSB MD: 00 0010 Rn 0010 Rn 0010 Rn 0011 Rn Rm 00MD CMP/EQ Rm, Rn 0011 Rn Rm 01MD DIV1 Rm, Rn 0011 Rn Rm 10MD SUB Rm, Rn 0011 Rn Rm 11MD ADD ...
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Section 2 CPU Instruction Code MSB LSB 0100 Rn Fx 1001 0100 Rm Fx 1010 0100 Rm/Rn Fx 1011 0100 Rn Rm 1100 0100 Rn Rm 1101 0100 Rm 00MD 1110 0100 Rm 01MD 1110 0100 Rm 10MD 1110 0100 ...
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Instruction Code MSB LSB 1100 00MD imm/disp 1100 01MD disp 1100 10MD imm 1100 11MD imm 1101 Rn disp 1110 Rn imm 1111 ************ Note: For details, refer to the SH-3/SH-3E/SH3-DSP Programming Manual. Fx: 0000 Fx: 0001 MD: 00 MD: ...
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Section 2 CPU Rev. 1.00 Dec. 27, 2005 Page 70 of 932 REJ09B0269-0100 ...
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Section 3 DSP Operating Unit 3.1 DSP Extended Functions This LSI incorporates a DSP unit and X/Y memory directly connected to the DSP unit. This LSI supports the DSP extended function instruction sets needed to control the DSP unit and ...
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Section 3 DSP Operating Unit instruction fields consist of two fields: field A and field B. In field A, a function for double data transfer instructions can be descried. In field B, ALU operation instructions and multiply instructions can be ...
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DSP Mode Resources 3.2.1 Processing Modes The CPU processing modes can be extended using the mode bit (MD) and DSP bit (DSP) of the status register (SR), as shown below. MD DSP Processing Mode 0 0 User mode 0 ...
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Section 3 DSP Operating Unit 3.2.3 CPU Register Sets In DSP mode, the status register (SR) in the CPU unit is extended to add control bits and three control registers: a repeat start register (SR), repeat end register (RE), and ...
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Initial Bit Bit Name Value 11 DMY 0 10 DMX 0 FR1 0 2 FR0 0 Note: When data is written to the SR register, 0 should be written ...
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Section 3 DSP Operating Unit • In privileged and privileged DSP modes, all SR bits can be modified. • In user DSP mode, the SR can be read by the STC instruction. • In user DSP mode, the LDC instruction ...
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Before entering the exception handling state, all bits including the DSP extension bits of the SR registers are saved in the SSR. Before returning from the exception handling, all bits including the DSP extension bits of the SR must be ...
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Section 3 DSP Operating Unit 3.3 CPU Extended Instructions 3.3.1 Repeat Control Instructions In DSP mode, a specific function is provided to execute repeat loops efficiently. By using this function, loop programs can be executed without overhead caused by the ...
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To control the repeat loop, the DSP extended control registers, such as the RE register and RS register and the RC[11:0] and RF[1:0] bits of the SR register, are used. These registers can be specified by the LDRE, LDRS, and ...
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Section 3 DSP Operating Unit • Example 2: Repeat loop consisting of three instructions LDRS RptStart +4 LDRE RptStart +4 SETRC #4 RptDtct: instr0 RptStart: instr1 Instr2 RptEnd: instr3 • Example 3: Repeat loop consisting of two instructions LDRS RptStart ...
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Example 4: Repeat loop consisting of one instruction LDRS RptStart +8 LDRE RptStart +4 SETRC #4 RptDtct: instr0 RptStart: RptEnd: instr1 In repeat loops consisting of three instructions, two instructions and one instruction, specific addresses are specified in the ...
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Section 3 DSP Operating Unit The rule is shown in table 3.3. Table 3.3 RS and RE Setting Rule 1 RS RptStart0 + 8 RE RptStart0 + 4 Note: The terms used above in table 3.3, are defined as follows. ...
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Table 3.5 Repeat Control Macros Instruction REPEAT RptStart, RptEnd, #imm Specifies RptStart as repeat start instruction, REPEAT RptStart, RptEnd, Rm Using the repeat macros shown in table 3.5, examples shown above can be simplified to examples 5 ...
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Section 3 DSP Operating Unit • Example 7: Repeat loop consisting of two instructions (extended to the instruction stream shown in example 3, above) REPEAT RptStart, RptEnd, #4 instr0 RptStart: instr1 RptEnd: instr2 • Example 8: Repeat loop consisting of ...
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Restrictions on Repeat Loop Control 1. Repeat control instruction assignment The SETRC instruction must be executed after executing the LDRS and LDRE instructions. In addition, note that at least one instruction is required between the SETRC instruction and a repeat ...
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Section 3 DSP Operating Unit 4. Restriction on branching to an instruction following the repeat detection instruction and an exception acceptance Execution of a repeat detection instruction must be completed without any branch so that the CPU can recognize the ...
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Program counter during repeat control If RC[11:0] ≥ 2, the program counter (PC) value is not correct for instructions two instructions following a repeat detection instruction repeat loop consisting of one to three instructions, the PC indicates ...
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Section 3 DSP Operating Unit 7. Repeat counter and repeat control The CPU always executes a program with comparing the repeat end register (RE) and the program counter (PC). If the PC matches the RE while the RC[11:0] bits of ...
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Example 1: Repeat loop consisting more instructions LDRS RptStart LDRE RptEnd LDRC #4 instr0 RptStart: instr1 ... ... ... ... instr(N-3) instr(N-2) instr(N-1) RptEnd: instrN • Example 2: Repeat loop consisting of three instructions LDRS RptStart ...
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Section 3 DSP Operating Unit • Example 3: Repeat loop consisting of two instructions LDRS RptStart LDRE RptEnd LDRC #4 instr0 RptStart: instr1 RptEnd: instr2 • Example 4: Repeat loop consisting of one instructions LDRS RptStart LDRE RptEnd LDRC #4 ...
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Table 3.8 Extended Repeat Control Instructions Instruction Operation LDRS @(disp,PC) Calculates (disp PC) and stores the result to the RS register LDRE @(disp,PC) Calculates (disp PC) and stores the result to the RE register ...
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Section 3 DSP Operating Unit BRA, BSR, BT/S, BF/S, BSRF, RTS, BRAF, RTE, JSR, JMP Repeat control instructions SETRC, LDRS, LDRE, LDRC Load instructions for SR, RS, and RE registers LCD Rn,SR, LDC @Rn+,SR, LDC Rn,RE, LDC @Rn+,RE, ...
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DSP Data Transfer Instructions In DSP mode, data transfer instructions are added for the DSP unit registers. The newly added instructions are classified into the following three groups. 1. Double data transfer instructions The DSP unit is connected to ...
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Section 3 DSP Operating Unit XAB [15:0] X memory Y memory [Legend] XAB: X bus (address) XDB: X bus (data) YAB: Y bus (address) YDB: Y bus (data) LAB: L bus (address) LDB: L bus (data) CDB: C bus (data) ...
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Double data transfer instructions can be described in parallel to the DSP operation instructions. Even if a conditional operation instruction is specified in parallel to a double data transfer instruction, the specified condition does not affect the data transfer operations. ...
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Section 3 DSP Operating Unit Table 3.9 Extended System Control Instructions in DSP Mode Instruction STS DSR,Rn STS A0,Rn STS X0,Rn STS X1,Rn STS Y0,Rn STS Y1,Rn STS.L DSR,@-Rn STS.L A0,@-Rn STS.L X0,@-Rn STS.L X1,@-Rn STS.L Y0,@-Rn STS.L Y1,@-Rn LDS.L ...
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General Registers The DSP instructions 10 general registers in the 16 general registers as address pointers or index registers for double data transfers and single data transfers. In the following descriptions, another register function in the DSP instructions is ...
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Section 3 DSP Operating Unit In assembler are used as symbols. In the DSP data transfer instructions, the following register names (alias) can also be used. In assembler, described as shown below. Ix: .REG (R8) Ix indicates ...
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DSP Data Addressing Table 3.10 shows the relationship between the double data transfer instructions and single data transfer instructions. Table 3.10 Overview of Data Transfer Instructions Double Data Transfer Instructions Single Data Transfer Instructions MOVX.W MOVY.W Address register Ax: ...
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Section 3 DSP Operating Unit decrement addressing mode. To perform decrementing, –2 is set in the index register and addition index register addressing is specified. When using X/Y data addressing, bit 0 of the address pointer is invalid. Accordingly, bit ...
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The LDC and STC instructions are extended for MOD register handling. If the DMX bit of the SR register is set, the modulo addressing is specified for the X address register. If the DMY bit of the ...
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Section 3 DSP Operating Unit An example of the use of modulo addressing is shown below. MOV.L #H’70047000,R10 LDC R10,MOD STC SR,R10 MOV.L #H’FFFFF3FF,R11 MOV.L #H’00000400,R12 AND R11,R10 OR R12,R10 LDC R10,SR MOV.L #H’A5007000,R14 MOVX.W @R4+,X0 MOVX.W @R4+,X0 MOVX.W @R4+,X0 ...
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Memory Data Formats Memory data formats that can be used in the DSP instructions are classified into word, and longword. An address error will occur if word data starting from an address other than 2n or longword data starting ...
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Section 3 DSP Operating Unit Table 3.12 Double Data Transfer Instruction Formats Type Mnemonic X memory NOPX data MOVX.W @Ax,Dx transfer MOVX.W @Ax+,Dx MOVX.W @Ax+Ix,Dx MOVX.W Da,@Ax MOVX.W Da,@Ax+ MOVX.W Da,@Ax+Ix Y memory NOPY data MOVY.W @Ay,Dy transfer MOVY.W @Ay+,Dy ...
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Table 3.13 Single Data Transfer Instruction Formats Type Mnemonic Single MOVS.W @-As,Ds data MOVS.W @As,Ds transfer MOVS.W @As+,Ds MOVS.W @As+Is,Ds MOVS.W Ds,@-As MOVS.W Ds,@As MOVS.W Ds,@As+ MOVS.W Ds,@As+Is MOVS.L @-As,Ds MOVS.L @As,Ds MOVS.L @As+,Ds MOVS.L @As+Is,Ds MOVS.L Ds,@-As MOVS.L Ds,@As ...
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Section 3 DSP Operating Unit 3.5 DSP Data Operation Instructions 3.5.1 DSP Registers This LSI has eight data registers (A0, A1, X0, X1, Y0, Y1, M0 and M1) and one control register (DSR) as DSP registers (figure 3.3). Four kinds ...
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Tables 3.14 and 3.15 show the data type of registers used in DSP instructions. Some instructions cannot use some registers shown in the tables because of instruction code limitations. For example, PMULS can use A1 as the source register, but ...
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Section 3 DSP Operating Unit Table 3.15 Source Register in DSP Operations Registers Instructions A0, A1 DSP Fixed-point, PDMSB, operation PSHA Integer Logical, PSHL, PMULS Data MOVX/Y.W, MOVS.W transfer MOVS.L A0G, A1G Data MOVS.W transfer MOVS.L X0, X1 DSP Fixed-point, ...
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Table 3.16 DSR Register Bits Initial Bits Bit Name Value 31 to — All TS2 to TS0 All R/W Function R Reserved Bits These bits ...
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Section 3 DSP Operating Unit Initial Bits Bit Name Value CS2 to All 0 CS0 Rev. 1.00 Dec. 27, 2005 Page 110 of 1044 REJ09B0269-0100 R/W Function R/W ...
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The DSR is assigned to the system registers. For the DSR, the following load and store instructions are supported. STS DSR,Rn; STS.L DSR,@-Rn; LDS Rn,DSR; LDS.L @Rn+,DSR; If the DSR is read by the STS instruction, upper bits (bits 31 ...
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Section 3 DSP Operating Unit Table 3.17 DSP Operation Instruction Formats Type Double data operation instructions Conditional single data operation instructions Unconditional single data operation instructions Table 3.18 Correspondence between DSP Instruction Operands and Registers ALU/Shift Operations Register Sx Sy ...
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PADD A0, M0, A0 DCF PINC M1, A1 PCMP M1, M0 Figure 3.6 Sample Parallel Instruction Program [ ] mean that the contents can be omitted. The no operation instructions NOPX and NOPY can be omitted. For details on the ...
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Section 3 DSP Operating Unit Table 3.19 DC Bit Update Definitions CS [2:0] Condition Mode Carry or borrow mode Negative value mode Zero value mode Overflow mode 1 ...
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Conditional Operations and Data Transfer Some instructions belonging to this class can be executed conditionally, as described earlier. The specified condition is valid only for the B field of the instruction, and is not valid for data transfer instructions ...
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Section 3 DSP Operating Unit Table 3.20 Examples of NOPX and NOPY Instruction Codes Instruction PADD X0,Y0,A0 MOVX.W @R4+,X0 MOVY.W @R6+R9,Y0 PADD X0,Y0,A0 NOPX PADD X0,Y0,A0 NOPX PADD X0,Y0,A0 NOPX PADD X0,Y0,A0 MOVX.W @R4+,X0 MOVY.W @R6+R9,Y0 MOVX.W @R4+,X0 NOPY MOVS.W ...
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DSP type fixed point With guard bits Without guard bits Multiplier input DSP type integer With guard bits Without guard bits Shift amount for arithmetic shift (PSHA) Shift amount for logical shift (PSHL) DSP type logical CPU type integer Longword ...
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Section 3 DSP Operating Unit 3.5.4 ALU Fixed-Point Operations Figure 3.9 shows the ALU arithmetic operation flow. Table 3.21 shows the variation of this type of operation and table 3.22 shows the correspondence between each operand and registers ...
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Table 3.21 Variation of ALU Fixed-Point Operations Mnemonic Function PADD Addition PSUB Subtraction PADDC Addition with carry PSUBC Subtraction with borrow PCMP Comparison PCOPY Data copy PABS Absolute PNEG Negation PCLR Clear Table 3.22 Correspondence between Operands and Registers Register ...
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Section 3 DSP Operating Unit Operation Sequence Example MOVX.W @(R4, R8), X0 PADD X0, Y0, A0 MOVX.W @R4+, X0 Slot 1 Stage IF MOVX ID EX MA/DSP Figure 3.10 Operation Sequence Example Every time an ALU arithmetic operation is executed, ...
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Example 1 Guard bits 0000 0000 1111 +) 0000 0000 0000 0000 0001 0000 0000 0000 0000 Carry is detected Example 3 Guard bits 0000 0000 0000 –) 0000 0000 0000 0000 0000 0000 0000 0000 0000 Borrow is not ...
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Section 3 DSP Operating Unit guard-bit parts, the DC bit is set. Even though guard bits are provided in the destination register, the DC bit always indicates the result of when no guard bits are provided. So, the DC bit ...
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The N bit always indicates the same state as the DC bit set in negative value mode by the CS[2:0] bits. See the negative value mode part above. The Z bit always indicates the same state as the DC bit ...
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Section 3 DSP Operating Unit Table 3.23 Variation of ALU Integer Operations Mnemonic Function PINC Increment by 1 PDEC Decrement by 1 Note: The ALU integer operations are basically 24-bit operation, the upper 16 bits of the base precision and ...
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ALU Logical Operations Figure 3.15 shows the ALU logical operation flow. Table 3.24 shows the variation of this type of operation. The correspondence between each operand and registers is the same as the ALU fixed- point operations as shown ...
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Section 3 DSP Operating Unit operation result. The definition of the DC bit is selected by the CS[2:0] (condition selection) bits in DSR. The DC bit result is: Carry or Borrow Mode: CS[2:0] = 000: The DC bit is always ...
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S Source 1 0 Figure 3.16 Fixed-Point Multiply Operation Flow Table 3.25 Variation of Fixed-Point Multiply Operation Mnemonic Function PMULS Signed multiplication Table 3.26 Correspondence between Operands and Registers Register Se A0 — A1 Yes M0 — M1 ...
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Section 3 DSP Operating Unit result is aligned to the LSB of the destination, but the fixed-point multiply operation result is aligned to the MSB, so that the LSB of the fixed-point multiply operation result is always 0. Multiply is ...
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Arithmetic Shift: Figure 3.17 shows the arithmetic shift operation flow. Left shift Shift out Shift amount data (source 2) Figure 3.17 Arithmetic Shift Operation Flow Note: The arithmetic shift operations are basically ...
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Section 3 DSP Operating Unit The DC bit is set when the operation result is a negative value, and cleared when the operation result is zero or a positive value. 3. Zero Value Mode: CS[2:0] = 010 The DC bit ...
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Logical Shift: Figure 3.18 shows the logical shift operation flow. Cleared to 0 Left shift Shift out Shift amount data (source 2) Figure 3.18 Logical Shift Operation Flow As shown in ...
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Section 3 DSP Operating Unit The DC bit is set when the operation result is zero; otherwise it is cleared. 4. Overflow Mode: CS[2:0] = 011 The DC bit is always cleared. 5. Signed Greater Than Mode: CS[2:0] = 100 ...
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Source Guard Priority encoder Guard 39 31 The definition of the DC bit is selected by the CS0–CS2 (condition selection) bits in DSR. The DC bit result is Carry or Borrow Mode: CS[2:0] = 000: ...
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Section 3 DSP Operating Unit Table 3.28 Operation Definition of PDMSB Source Data Guard Bit Upper Word 39 38 … … … … ...
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Table 3.29 Variation of PDMSB Operation Mnemonic Function PDMSB MSB detection The N bit always indicates the same state as the DC bit set in negative value mode by the CS[2:0] bits. See the negative value mode part above. The ...
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Section 3 DSP Operating Unit 31 39 Source Guard Guard 39 Figure 3.20 Rounding Operation Flow Figure 3.21 Definition of Rounding Operation Table 3.30 Variation of Rounding Operation Mnemonic Function PRND Rounding • Overflow Protection The S ...
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Overflow Protection The S bit effective for any arithmetic operations executed in the DSP unit, including the SH's standard multiply and MAC operations. The S bit used as the overflow protection enable bit. ...
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Section 3 DSP Operating Unit 3.5.12 Local Data Move Instruction The DSP unit of this LSI provides additional two independent registers, MACL and MACH, in order to support CPU standard multiply/MAC operations. They can be also used as temporary storage ...
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Operand Conflict When an identical destination operand is specified with multiple parallel instructions, data conflict occurs. Table 3.34 shows the correspondence between each operand and registers. Table 3.34 Correspondence between Operands and Registers X-Memory Load DSP ...
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Section 3 DSP Operating Unit 3.6 DSP Extended Function Instruction Set 3.6.1 CPU Extended Instructions Table 3.35 DSP Mode Extended System Control Instructions Instruction Instruction Code Operation SETRC #imm 10000010iiiiiiii SETRC Rn 0100nnnn00010100 LDRS @(disp,PC) 10001100dddddddd LDRE @(disp,PC) 10001110dddddddd STC ...
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Instruction Instruction Code Operation LDS.L @Rn + ,Y0 0100nnnn10100110 LDS.L @Rn + ,Y1 0100nnnn10110110 LDC.L @Rn + ,MOD 0100nnnn01010111 LDC.L @Rn + ,RS 0100nnnn01100111 LDC.L @Rn + ,RE 0100nnnn01110111 LDS Rn,DSR 0100nnnn01101010 LDS Rn,A0 0100nnnn01111010 LDS Rn,X0 0100nnnn10001010 LDS Rn,X1 ...
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Section 3 DSP Operating Unit 3.6.2 Double-Data Transfer Instructions Table 3.36 Double Data Transfer Instruction Instruction X memory NOPX data MOVX.W @Ax,Dx transfer MOVX.W @Ax + ,Dx MOVX.W @Ax + Ix,Dx MOVX.W Da,@Ax MOVX.W Da,@Ax + MOVX.W Da,@ ...
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Single-Data Transfer Instructions Table 3.37 Single Data Transfer Instructions Instruction Instruction Code MOVS.W @-As,Ds 111101AADDDD0000 As-2 MOVS.W @As,Ds 111101AADDDD0100 (As) MOVS.W @As + ,Ds 111101AADDDD1000 (As) MOVS.W @As + Ix,Ds 111101AADDDD1100 (As) MOVS.W Ds,@-As 111101AADDDD0001 As-2 MOVS.W Ds,@As 111101AADDDD0101 ...
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Section 3 DSP Operating Unit Table 3.38 Correspondence between DSP Data Transfer Operands and Registers Register register R1 R2 (As2) R3 (As3) R4 (Ax0) Yes R5 (Ax1) Yes R6 (Ay0) R7 (Ay1) R8 (Ix) R9 (Iy) DSP ...
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DSP Operation Instructions Table 3.39 DSP Operation Instructions Instruction Instruction Code Operation PMULS Se,Sf,Dg 111110********** 0100eeff0000gg00 PADD Sx,Sy,Du 111110********** PMULS Se,Sf,Dg 0111eeffxxyygguu PSUB Sx,Sy,Du 111110********** PMULS Se,Sf,Dg 0110eeffxxyygguu PADD Sx,Sy,Dz 111110********** 10110001xxyyzzzz DCT PADD 111110********** Sx,Sy,Dz 10110010xxyyzzzz DCF PADD ...
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Section 3 DSP Operating Unit Instruction Instruction Code Operation PSHL Sx,Sy,Dz 111110********** 10000001xxyyzzzz DCT PSHL 111110********** Sx,Sy,Dz 10000010xxyyzzzz DCF PSHL 111110********** Sx,Sy,Dz 10000011xxyyzzzz PCOPY Sx,Dz 111110********** 11011001xx00zzzz PCOPY Sy,Dz 111110********** 1111100100yyzzzz DCT PCOPY Sx,Dz 111110********** 11011010xx00zzzz DCT PCOPY 111110********** Sy,Dz ...
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Instruction Instruction Code Operation PINC Sx,Dz 111110********** 10011001xx00zzzz PINC Sy,Dz 111110********** 1011100100yyzzzz DCT PINC Sx,Dz 111110********** 10011010xx00zzzz DCT PINC Sy,Dz 111110********** 1011101000yyzzzz DCF PINC Sx,Dz 111110********** 10011011xx00zzzz DCF PINC Sy,Dz 111110********** 1011101100yyzzzz PNEG Sx,Dz 111110********** 11001001xx00zzzz PNEG Sy,Dz 111110********** 1110100100yyzzzz ...
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Section 3 DSP Operating Unit Instruction Instruction Code Operation PAND Sx,Sy,Dz 111110********** 10010101xxyyzzzz DCT PAND 111110********** Sx,Sy,Dz 10010110xxyyzzzz DCF PAND 111110********** Sx,Sy,Dz 10010111xxyyzzzz PXOR Sx,Sy,Dz 111110********** 10100101xxyyzzzz DCT PXOR 111110********** Sx,Sy,Dz 10100110xxyyzzzz DCF PXOR 111110********** Sx,Sy,Dz 10100111xxyyzzzz PDEC Sx,Dz 111110********** ...
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Instruction Instruction Code Operation PSHA #imm,Dz 111110********** 00010iiiiiiizzzz PSHL #imm,Dz 111110********** 00000iiiiiiizzzz PSTS MACH,Dz 111110********** 110011010000zzzz DCT PSTS 111110********** MACH,Dz 110011100000zzzz DCF PSTS 111110********** MACH,Dz 110011110000zzzz PSTS MACL,Dz 111110********** 110111010000zzzz DCT PSTS 111110********** MACL,Dz 110111100000zzzz DCF PSTS 111110********** MACL,Dz 110111110000zzzz ...
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Section 3 DSP Operating Unit Instruction Instruction Code Operation PSUBC Sx,Sy, Dz 111110********** 10100000xxyyzzzz PCMP Sx,Sy 111110********** 10000100xxyy0000 PABS Sx,Dz 111110********** 10001000xx00zzzz PABS Sy,Dz 111110********** 1010100000yyzzzz PRND Sx,Dz 111110********** 10011000xx00zzzz PRND Sy,Dz 111110********** 1011100000yyzzzz Note: See table 3.19. * Rev. ...
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Operation Code Map in DSP Mode Table 3.40 shows the operation code map including an instruction codes extended in the DSP mode. Table 3.40 Operation Code Map Instruction Code Fx: 0000 MSB LSB MD: 00 0000 Rn Fx 0000 ...
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Section 3 DSP Operating Unit Instruction Code Fx: 0000 MSB LSB MD: 00 0000 Rn Rm 11MD MOV. B @(R0, Rm), Rn 0001 Rn Rm disp MOV.L Rm, @(disp:4, Rn) 0010 Rn Rm 00MD MOV.B Rm, @Rn 0010 Rn Rm ...
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Instruction Code Fx: 0000 MSB LSB MD: 00 0100 Rm 00MD 0111 LDC.L @Rm+, SR 0100 Rm 01MD 0111 LDC.L @Rm+, SPC 0100 Rm 10MD 0111 LDC.L @Rm+, R0_BANK 0100 Rm 11MD 0111 LDC.L @Rm+, R4_BANK 0100 Rn Fx 1000 ...
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Section 3 DSP Operating Unit Instruction Code Fx: 0000 MSB LSB MD: 00 1000 01MD Rm disp MOV.B @(disp:4, Rm), R0 1000 10MD imm/disp CMP/EQ #imm:8, R0 1000 11MD imm/disp LDRS @(disp:8,PC) 1001 Rn disp MOV.W 1010 disp BRA 1011 ...
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Section 4 Exception Handling Exception handling is separate from normal program processing, and is performed by a routine separate from the normal program. For example attempt is made to execute an undefined instruction code or an instruction protected ...
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Section 4 Exception Handling Figure 4.1 shows the bit configuration of each register Figure 4.1 Register Bit Configuration 4.1.1 TRAPA Exception Register (TRA) TRA is assigned to address H′FFFFFFD0 and consists of the 8-bit immediate ...