HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 587

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bit
4
3
2
Bit Name
RE
REIE

Initial
Value
0
0
0
R/W
R/W
R
R/W
Section 16 Serial Communication Interface with FIFO (SCIF)
Description
Receive Enable
Enables or disables the start of serial reception by the
SCIF.
0: Reception disabled*
1: Reception enabled*
Notes: 1. Clearing the RE bit to 0 does not affect
Receive Error Interrupt Enable
Enables or disables generation of receive-error
interrupt (ERI) request and break interrupt (BRI)
request. The REIE bit setting is available when the
RIE bit is cleared to 0.
0: Receive-error interrupt (ERI) request and break
1: Receive-error interrupt (ERI) request and break
Note: * A receive-error interrupt (ERI) request and
Reserved
This bit is always read as 0. The write value should
always be 0.
interrupt (BRI) request disabled*
interrupt (BRI) request enabled
2. SCSMR and SCFCR settings must be
break interrupt (BRI) request can be cleared
by reading 1 from the ER, BRK, and ORER
flags, then clearing the flags to 0, or by
clearing the RIE and REIE bits to 0.
Even if the RIE bit is cleared to 0, setting
the REIE bit to 1 enables generation of the
ERI and BRI requests. This setting is
achieved to notify the ERI and BRI requests
to the interrupt controller at the DMAC
transfer.
the DR, ER, BRK, RDF, FER, PER, and
ORER flags, which retain their state.
made, the receive format decided, and the
receive FIFO reset, before the RE bit is
set to 1.
Rev. 1.00 Dec. 27, 2005 Page 543 of 932
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