HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 79

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 2 CPU
2.3.1
General Registers
There are twenty-four 32-bit general registers: R0_BANK0 to R7_BANK0, R0_BANK1 to
R7_BANK1, and R8 to R15. R0 to R7 are banked. The process mode and the register bank (RB)
bit in the status register (SR) define which set of banked registers (R0_BANK0 to R7_BANK0 or
R0_BANK1 to R7_BANK1) are accessed as general registers. R0 to R7 registers in the selected
bank are accessed as R0 to R7. R0 to R7 in the non-selected bank is accessed as R0_BANK to
R7_BANK by the control register load instruction (LDC) and control register store instruction
(STC).
In user mode, bank 0 is selected regardless of he RB bit value. Sixteen registers: R0_BANK0 to
R7_BANK0 and R8 to R15 are accessed as general registers R0 to R15. The R0_BANK1 to
R7_BANK1 registers in bank 1 cannot be accessed.
In privileged mode that is entered by a transition to exception handling state, the RB bit is set to 1
to select bank 1. In privileged mode, sixteen registers: R0_BANK1 to R7_BANK1 and R8 to R15
are accessed as general registers R0 to R15. A bank is switched automatically when an exception
handling state is entered, registers R0 to R7 need not be saved by the exception handling routine.
The R0_BANK0 to R7_BANK0 registers in bank 0 can be accessed as R0_BANK to R7_BANK
by the LDC and STC instructions.
In privileged mode, bank 0 can also be used as general registers by clearing the RB bit to 0. In this
case, sixteen registers: R0_BANK0 to R7_BANK0 and R8 to R15 are accessed as general
registers R0 to R15. The R0_BANK1 to R7_BANK1 registers in bank 1 can be accessed as
R0_BANK to R7_BANK by the LDC and STC instructions.
The general registers R0 to R15 are used as equivalent registers for almost all instructions. In
some instructions, the R0 register is automatically used or only the R0 register can be used as
source or destination registers.
Rev. 1.00 Dec. 27, 2005 Page 35 of 932
REJ09B0269-0100