HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 662

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 17 Serial I/O with FIFO (SIOF)
Figure 17.5 shows the transmit/receive data and the SITDR and SIRDR bit alignment.
Note: In the figure, only the shaded areas are transmitted or received as valid data. Data in
Monaural or stereo can be specified for transmit data by the TDLE bit and TDRE bit in SITDAR.
Monaural or stereo can be specified for receive data by the RDLE bit and RDRE bit in SIRDAR.
To achieve left and right same audio output while stereo is specified for the transmit data, specify
the TLREP bit in SITDAR. Tables 17.5 and 17.6 show the audio mode specification for transmit
data and that for receive data, respectively. To execute 8-bit monaural transmission or reception,
use the left channel.
Rev. 1.00 Dec. 27, 2005 Page 618 of 932
REJ09B0269-0100
unshaded areas is not transmitted or received.
(a) 16-bit stereo data
(b) 16-bit monaural data
(c) 8-bit monaural data
(d) 16-bit stereo data (left and right same audio output) data
Figure 17.5 Transmit/Receive Data Bit Alignment
31
31
31
31
Data
Lch.data
24 23
24 23
24 23
24 23
Data
Data
16 15
16 15
16 15
16 15
Rch.data
8 7
8 7
8 7
8 7
0
0
0
0