HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 203

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

4.2
4.2.1
In exception handling, the contents of the program counter (PC) and status register (SR) are saved
in the saved program counter (SPC) and saved status register (SSR), respectively, and execution of
the exception handler is invoked from a vector address. By executing the return from exception
handler (RTE) in the exception handler routine, it restores the contents of PC and SR, and returns
to the processor state at the point of interruption and the address where the exception occurred.
A basic exception handling sequence consists of the following operations. If an exception occurs
and the CPU accepts it, operations 1 to 8 are executed.
1. The contents of PC is saved in SPC.
2. The contents of SR is saved in SSR.
3. The block (BL) bit in SR is set to 1, masking any subsequent exceptions.
4. The mode (MD) bit in SR is set to 1 to place the privileged mode.
5. The register bank (RB) bit in SR is set to 1.
6. An exception code identifying the exception event is written to bits 11–0 of the exception
7. If a TRAPA instruction is executed, an 8-bit immediate data specified by the TRAPA
8. Instruction execution jumps to the designated exception vector address to invoke the handler
The above operations from 1 to 8 are executed in sequence. During these operations, no other
exceptions may be accepted unless multiple exception acceptance is enabled.
In an exception handling routine for a general exception, the appropriate exception handling must
be executed based on an exception source determined by the EXPEVP. In an interrupt exception
handling routine, the appropriate exception handling must be executed based on an exception
source determined by the INTEVT or INTEVT2. After the exception handling routine has been
completed, program execution can be resumed by executing an RTE instruction. The RTE
instruction causes the following operations to be executed.
1. The contents of the SSR are restored into the SR to return to the processing state in effect
2. A delay slot instruction of the RTE instruction is executed.*
event (EXPEVT) or interrupt event (INTEVT or INTEVT2) register.
instruction is set to TRA. For an exception related to memory accesses, the logic address
where the exception occurred is written to TEA. *
routine.
before the exception handling took place.
Exception Handling Function
Exception Handling Flow
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Rev. 1.00 Dec. 27, 2005 Page 159 of 932
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Section 4 Exception Handling
REJ09B0269-0100