HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 107

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Table 2.11 System Control Instructions
Instruction
CLRMAC
CLRS
CLRT
LDC
LDC
LDC
LDC
LDC
LDC
LDC
LDC
LDC
LDC
LDC
LDC
LDC
LDC.L
LDC.L
LDC.L
LDC.L
LDC.L
LDC.L
LDC.L
LDC.L
LDC.L
Rm,SR
Rm,GBR
Rm,VBR
Rm,SSR
Rm,SPC
Rm,R0_BANK
Rm,R1_BANK
Rm,R2_BANK
Rm,R3_BANK
Rm,R4_BANK
Rm,R5_BANK
Rm,R6_BANK
Rm,R7_BANK
@Rm+,SR
@Rm+,GBR
@Rm+,VBR
@Rm+,SSR
@Rm+,SPC
@Rm+,
R0_BANK
@Rm+,
R1_BANK
@Rm+,
R2_BANK
@Rm+,
R3_BANK
Instruction Code
0000000000101000
0000000001001000
0000000000001000
0100mmmm00001110
0100mmmm00011110
0100mmmm00101110
0100mmmm00111110
0100mmmm01001110
0100mmmm10001110
0100mmmm10011110
0100mmmm10101110
0100mmmm10111110
0100mmmm11001110
0100mmmm11011110
0100mmmm11101110
0100mmmm11111110
0100mmmm00000111
0100mmmm00010111
0100mmmm00100111
0100mmmm00110111
0100mmmm01000111
0100mmmm10000111
0100mmmm10010111
0100mmmm10100111
0100mmmm10110111
Operation
0→MACH,MACL
0→S
0→T
Rm→SR
Rm→GBR
Rm→VBR
Rm→SSR
Rm→SPC
Rm→R0_BANK
Rm→R1_BANK
Rm→R2_BANK
Rm→R3_BANK
Rm→R4_BANK
Rm→R5_BANK
Rm→R6_BANK
Rm→R7_BANK
(Rm)→SR, Rm+4→Rm
(Rm)→GBR, Rm+4→Rm
(Rm)→VBR, Rm+4→Rm
(Rm)→SSR,Rm+4→Rm
(Rm)→SPC,Rm+4→Rm
(Rm)→R0_BANK,Rm+4→Rm
(Rm)→R1_BANK,Rm+4→Rm
(Rm)→R2_BANK,Rm+4→Rm
(Rm)→R3_BANK, Rm+4→Rm √
Rev. 1.00 Dec. 27, 2005 Page 63 of 932
Privileged
Mode



√

√
√
√
√
√
√
√
√
√
√
√
√

√
√
√
√
√
√
REJ09B0269-0100
Cycles
1
1
1
6
4
4
4
4
4
4
4
4
4
4
4
4
8
4
4
4
4
4
4
4
4
Section 2 CPU
T Bit


0
LSB












LSB







