10020EV8-4F NXP Semiconductors, 10020EV8-4F Datasheet
10020EV8-4F
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10020EV8-4F Summary of contents
Page 1
... The SNAP design software package from Philips Semiconductors simplifies design entry based upon Boolean or state equations. The 10H20EV8/10020EV8 is a two-level logic element comprised of 11 fixed inputs, an input pin that can either be used as a clock or 12th input, 90 AND gates, and 8 Output Logic Macrocells ...
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... NOTES: 1. All unprogrammed or virgin “AND” gate locations are pulled to logic “0” 2. Programmable connections 3. Pinout for F Package October 22, 1993 INPUT LINES 114 Product specification 10H20EV8/10020EV8 OUTPUT 4 LOGIC MACRO CELL OUTPUT 21 LOGIC MACRO CELL OUTPUT 5 LOGIC MACRO CELL OUTPUT 20 LOGIC ...
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... The 10H20EV8/10020EV8 incorporates an extremely versatile Output Logic Macrocell that allows the user complete flexibility when configuring outputs. As seen in Figure 1, the 10H20EV8/ 10020EV8 Output Logic Macrocell consists of an edge-triggered D-type flip-flop, an output select MUX, and a feedback select MUX. Fuses S and S allow the user to select ...
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... Supply voltage (negative High level input voltage IH V Low level input voltage IL T Operating ambient temperature range amb NOTE: When operating at other than the specified OPERATING CONDITIONS 10020EV8 SYMBOL PARAMETER Circuit ground CC CO1 CO2 V Supply voltage EE V Supply voltage when opetating with the 10K ...
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... LOW, even though the Q output of all flip-flops would go HIGH. A Reset signal would force the opposite conditions. PRELOAD To simplify testing, the 10H20EV8/10020EV8 has also included PRELOAD circuitry. This allows a user to load any particular data desired into the registers regardless of the programmed pattern. This means that the ...
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... PARAMETER V High level output voltage OH V Low level output voltage OL I High level input current IH I Low level input current IL –I Supply current EE DC ELECTRICAL CHARACTERISTICS 10020EV8 +85 C, –4.8V V –4.2V, V amb SYMBOL PARAMETER V High level output voltage OH V High level output threshold voltage ...
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... Philips Semiconductors Programmable Logic Devices ECL programmable array logic AC ELECTRICAL CHARACTERISTICS (for Ceramic Dual In-Line Package) 10H20EV8 + –5.2V amb EE 10020EV8 +85 C, –4.8V V amb EE SYMBOL PARAMETER FROM Pulse Width t Clock High CLK + CKH t Clock Low CLK – CKL t Clock Period CLK + CKP ...
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... Philips Semiconductors Programmable Logic Devices ECL programmable array logic AC ELECTRICAL CHARACTERISTICS (for Plastic Leaded Chip Carrier) 10H20EV8 + –5.2V amb EE 10020EV8 +85 C, –4.8V V amb EE SYMBOL PARAMETER FROM Pulse Width t Clock High CLK + CKH t Clock Low CLK – CKL t Clock Period CLK + CKP ...
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... DUT CLK 0.01 F –2.5V + 0.010V FOR 10020EV8 –3.2V + 0.010V FOR 10H20EV8 , and 0.01 F and 25 F from GND the distance from the DUT pin to the junction of the cable from the Pulse inch (6mm inch (6mm) in length (refer to section on AC setup procedure better. ...
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... CO1 CO2 AMPLITUDE REP RATE PULSE WIDTH TLH 740mV 1MHz 500ns 0.7 + 0.1ns P–P Input Pulse Definition 122 Product specification 10H20EV8/10020EV8 +1110mV (10H20EV8) +1050mV (10020EV8) +310mV +1110mV (10H20EV8) +1050mV (10020EV8) +310mV = GND (0V) t THL 1.3 + 0.2ns = GND (0V) t THL 0.7 + 0.1ns ...
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... TIMING DIAGRAMS I, I/O 50% (INPUT) CLK I/O (REGISTERED OUTPUT) I/O (COMBINATORIAL OUTPUT) 0V REGISTERED ACTIVE-LOW OUTPUT I, I/O (INPUT) October 22, 1993 50 50% 50% t CKH CKO P 50 50% Flip-Flop and Gate Outputs V = –4.94 10H20EV8 –4.2 10020EV8 PPR 50 CLK 50% 50% Power-On Reset 123 Product specification 10H20EV8/10020EV8 50% t CKL ...
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... Philips Semiconductors Programmable Logic Devices ECL programmable array logic TIMING DIAGRAMS (Continued) I, I/O 50% (INPUT) I/O (OUTPUT) CLK ASYNCHRONOUS PRESET/RESET I/O (OUTPUT) October 22, 1993 t OD 50% Output Enable/Disable 50% t PRH t PRO 50% Asynchronous Preset/Reset 124 Product specification 10H20EV8/10020EV8 50 50% 50% t PRS 50% ...
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... Philips Semiconductors Programmable Logic Devices ECL programmable array logic REGISTER PRELOAD The 10H20EV8/10020EV8 has included circuitry that allows a user to load data into the output registers. Register PRELOAD can be done at any time and is not dependent on any particular pattern programmed into the device. This simplifies the ability to fully verify logic states and sequences even after the device has been patterned ...
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... CUPL is a trademark of Logical Devices, Inc. October 22, 1993 All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format. 10H20EV8/10020EV8 logic designs can also be generated using the program table entry format detailed on the following page. This ...
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... Philips Semiconductors Programmable Logic Devices ECL programmable array logic PROGRAM TABLE T AND PIN October 22, 1993 CONTROL WORD POLARITY OR (FIXED) F(I) F( 127 Product specification 10H20EV8/10020EV8 ...
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... PS/2, or any compatible system with DOS 2.1 or higher. A minimum of 640K bytes of RAM is required together with a hard disk. DESIGN SECURITY The 10H20EV8/10020EV8 has a programmable security fuse that controls the access to the data programmed in the device. By using this programmable feature, proprietary designs implemented in the ...
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... LOGIC MACROCELL MACROCELL MACROCELL OUTEV8 OUTEV8 OUTEV8 OUTPUT OLMREG SELECT MUX S S CLK FEEDBACK MUX Output Logic Macrocell 129 Product specification 10H20EV8/10020EV8 I 11 NINEV8 DINEV8 AND OUTPUT OUTPUT LOGIC LOGIC PRESET MACROCELL MACROCELL OUTEV8 OUTEV8 OUTEV8 OUTEV8 F n OLMDIR V CC OLMINV ...