CY7C346-35NC Cypress Semiconductor Corporation., CY7C346-35NC Datasheet
CY7C346-35NC
Specifications of CY7C346-35NC
Related parts for CY7C346-35NC
CY7C346-35NC Summary of contents
Page 1
... Each LAB is interconnected through the programmable inter- connect array, allowing all signals to be routed throughout the chip. The speed and density of the CY7C346 allow used in a wide range of applications, from replacement of large amounts of 7400-series TTL logic, to complex controllers and multifunction chips. With greater than 25 times the functionality of 20-pin PLDs, the CY7C346 allows the replacement of over 50 TTL devices ...
Page 2
... I/O I/O I/O INP V INP GND INP I/O CC I/O I/O I/O I/O INP V INP INP INP INP CY7C346 Unit I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND I/O I/O I/O I/O I I/O I/O I/O I/O ...
Page 3
... INPUT 20 INPUT 21 INPUT 22 I/O 23 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I Document #: 38-03005 Rev. *B USE ULTRA37000 FOR TM ALL NEW DESIGNS PQFP Top View CY7C346 CY7C346 I I/O I I/O I/O 75 I/O 74 I/O 73 INPUT 72 INPUT 71 INPUT INPUT 67 INPUT 66 INPUT 65 INPUT 64 GND 63 GND ...
Page 4
... Logic Array Blocks There are eight logic array blocks in the CY7C346. Each LAB consists of a macrocell array containing 16 macrocells, an expander product term array containing 32 expanders, and an I/O block. The LAB is fed by the programmable interconnect array and the dedicated input bus. All macrocell feedbacks go to the macrocell array, the expander array, and the program- mable interconnect array ...
Page 5
... The bit that controls this function, along with all other program data, may be reset simply by erasing the entire device. The CY7C346 is fully functionally tested and guaranteed through complete testing of each programmable EPROM bit and all internal logic elements thus ensuring 100% programming yield ...
Page 6
... C (Case) Min. 2.4 2.2 V –0.3 –10 –40 [3, 4] –30 Commercial Military/Industrial Commercial Military/Industrial Max ALL INPUT PULSES 3.0V 90% 10% GND ≤ 0.5V has been chosen to avoid OUT CY7C346 ± ± 10% 5V ± 10% Max. Unit 0.8 V µA +10 µA +40 –90 mA 225 mA 275 ...
Page 7
... Document #: 38-03005 Rev. *B USE ULTRA37000 TM ALL NEW DESIGNS Description [7] [10] [4, 7] [4, 7] [7] [7] [4, 7] [4, 7] [7] [4, 7] [4, 7] [7] [4, 15] [4] ) MAX3 [4, 16 CO1 S1 [4, 17 )), WL WH [4, 18] ) [4, 19 [4, 20] FOR CY7C346 [6] Over Operating Range 7C346-25 7C346-30 7C346-35 Min. Max. Min. Max. Min 12 12.5 ...
Page 8
... If register output states must also control external points, this frequency can ACF AS1 AWH AWL . ACO1 . It assumes data and clock input signals are applied to dedicated input pins and no expander logic is used. ACO1 FOR CY7C346 [6] Over Operating Range 7C346-25 7C346-30 7C346-35 Min. Max. Min. Max. ...
Page 9
... This specification guarantees the maximum combinatorial delay associated with the macrocell register bypass when the macrocell is configured for combinatorial operation. Document #: 38-03005 Rev. *B USE ULTRA37000 FOR TM ALL NEW DESIGNS 7C346-25 Min. Max [28 [29 CY7C346 Over Operating Range 7C346-30 7C346-35 Min. Max. Min. Max ...
Page 10
... Input Document #: 38-03005 Rev. *B USE ULTRA37000 TM ALL NEW DESIGNS Description [7] [10] [11] [4, 12] [4, 7] [4, 7] [4, 13] [7, 14] [7] [4, 7] [4, 7] [7] [ [7] [4, 15] [4] )) MAX3 [ CO1 + WL [ CO1 FOR CY7C346 [6] Over Operating Range 7C346-30 7C346-35 Min. Max. Min. Max 12 ...
Page 11
... AOH [4, 27] Input Document #: 38-03005 Rev. *B USE ULTRA37000 TM ALL NEW DESIGNS Description Min. [7] [20] [7] [7] [7] [7, 21] [4, 22] [4] )) MAXA4 27.7 [4, 23 ACO1 AS1 [4, 24] 33.3 [4, 26 AWL FOR CY7C346 [6] Over Operating Range 7C346-30 7C346-35 Max. Min. Max 23.2 40 33.3 28.5 40 33.3 ...
Page 12
... Asynchronous Preset and Clear Pulse Width PCW t Asynchronous Preset and Clear Recovery Time PCR t Programmable Interconnect Array Delay Time PIA Document #: 38-03005 Rev. *B USE ULTRA37000 TM ALL NEW DESIGNS Over Operating Range Description Min. [28] [29] FOR CY7C346 7C346-30 7C346-35 Max. Min. Max ...
Page 13
... REGISTERED FEEDBACK ASYNCHRONOUS CLOCK INPUT ASYNCHRONOUS CLEAR/PRESET ASYNCHRONOUS REGISTERED OUTPUTS COMBINATORIAL OUTPUT FROM ASYNCHRONOUS REGISTERED FEEDBACK Document #: 38-03005 Rev. *B USE ULTRA37000 FOR TM ALL NEW DESIGNS [7] [10 PD1 PD2 [ [ CO1 CO2 AS1 t ACO1 AOH ACO2 CY7C346 HIGH-IMPEDANCE THREE-STATE VALID OUTPUT AWH AWL Page ...
Page 14
... REGISTER OUTPUT TO ANOTHER LAB Internal Synchronous SYSTEM CL OCK PIN t IN SYSTEM CL OCK AT REGISTER t RSU DATA FROM LOGIC ARRAY Document #: 38-03005 Rev. *B USE ULTRA37000 FOR TM ALL NEW DESIGNS PIA EXP t AWL RSU LATCH FD t PIA ICS t RH CY7C346 LAC LAD CLR PRE FD Page ...
Page 15
... Switching Waveforms (continued) Internal Synchronous CLOCK FROM LOGIC ARRAY DATA FROM LOGIC ARRAY OUTPUT PIN Document #: 38-03005 Rev. *B USE ULTRA37000 TM ALL NEW DESIGNS FOR CY7C346 HIGH IMPEDANCE STATE Page ...
Page 16
... AWL Ordering Information Speed (ns) Ordering Code 25 CY7C346-25HC/HI CY7C346-25JC/JI CY7C346-25NC/NI CY7C346-25RC/RI 30 CY7C346-30HC/HI CY7C346-30JC/JI CY7C346-30NC/NI CY7C346-30HMB CY7C346-30RMB Document #: 38-03005 Rev. *B USE ULTRA37000 TM ALL NEW DESIGNS Subgroups Subgroups Package Name Package Type H84 84-pin Windowed Leaded Chip Carrier J83 84-lead Plastic Leaded Chip Carrier ...
Page 17
... Ordering Information (continued) Speed (ns) Ordering Code 35 CY7C346-35JC/JI CY7C346-35NC/NI CY7C346-35RC/RI CY7C346-35HMB CY7C346-35RMB Package Diagrams Document #: 38-03005 Rev. *B USE ULTRA37000 TM ALL NEW DESIGNS Package Name Package Type J83 84-lead Plastic Leaded Chip Carrier N100 100-lead Plastic Quad Flatpack R100 100-pin Windowed Ceramic Pin Grid Array ...
Page 18
... Package Diagrams (continued) Document #: 38-03005 Rev. *B USE ULTRA37000 FOR TM ALL NEW DESIGNS 84-Lead Plastic Leaded Chip Carrier J83 CY7C346 51-85006-*A Page ...
Page 19
... Package Diagrams (continued) Document #: 38-03005 Rev. *B USE ULTRA37000 FOR TM ALL NEW DESIGNS 100-Lead Plastic Quad Flatpack N100 CY7C346 51-85052-*A Page ...
Page 20
... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. USE ULTRA37000 TM FOR ALL NEW DESIGNS 100-Pin Windowed Ceramic Pin Grid Array R100 CY7C346 51-80010-*C Page ...
Page 21
... Document History Page Document Title: CY7C346 128-Macrocell MAX® EPLD Document Number: 38-03005 REV. ECN NO. Issue Date ** 106270 04/23/01 *A 113614 04/11/02 *B 213375 See ECN Document #: 38-03005 Rev. *B USE ULTRA37000 FOR TM ALL NEW DESIGNS Orig. of Change SZV Change from Spec number 38-00244 to 38-03005 ...