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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Presettable 4-Bit Down Counters
constructed with MOS P–channel and N–channel enhancement mode
devices in a monolithic structure.
with a decoded “0” state output for divide–by–N applications. In single stage
applications the “0” output is applied to the Preset Enable input. The
Cascade Feedback input allows cascade divide–by–N operation with no
additional gates required. The Inhibit input allows disabling of the pulse
counting function. Inhibit may also be used as a negative edge clock.
ers, phase–locked loops, and other frequency division applications requiring
low power dissipation and/or high noise immunity.
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
X = Don’t Care
NOTES:
REV 3
1/94
MAXIMUM RATINGS*
V in , V out
Clock Reset
** Output “0” is high when reset is low, only if CF is high and count is 0000.
Symbol
MOTOROLA CMOS LOGIC DATA
I in , I out
* Output “0” is low when reset goes high only it PE and CF are low.
The MC14522B BCD counter and the MC14526B binary counter are
These devices are presettable, cascadable, synchronous down counters
These complementary MOS counters can be used in frequency synthesiz-
Motorola, Inc. 1995
V DD
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Logic Edge–Clocked Design — Incremented on Positive Transition of
Clock or Negative Transition of Inhibit
Asynchronous Preset Enable
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
X
X
X
X
X
X
X
H
H
H
H
T stg
L
L
P D
T L
Plastic “P and D/DW” Packages: – 7.0 mW/ _ C From 65 _ C To 125 _ C
Ceramic “L” Packages: – 12 mW/ _ C From 100 _ C To 125 _ C
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
DC Supply Voltage
Input or Output Voltage (DC or Transient)
Input or Output Current (DC or Transient),
per Pin
Power Dissipation, per Package†
Storage Temperature
Lead Temperature (8–Second Soldering)
Inhibit
X
X
X
X
X
X
X
H
L
L
L
L
Inputs
(Voltages Referenced to V SS )
Enable
Preset
Parameter
H
H
X
X
H
L
L
L
L
L
L
L
L
L
L
L
L
L
FUNCTION TABLE
Feedback
Cascade
H
H
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
Output
“0”
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
– 0.5 to V DD + 0.5
– 0.5 to + 18.0
Asynchronous reset*
Asynchronous reset*
Asynchronous reset
Asynchronous reset
Asynchronous reset
Asynchronous reset
Asynchronous preset
Decrement inhibited
Decrement inhibited
Decrement inhibited
No change** (inactive edge)
No change** (inactive edge)
No change** (inactive edge)
No change** (inactive edge)
Decrement**
Decrement**
Decrement**
Decrement**
– 65 to + 150
Value
500
260
10
Resulting
Resulting
Function
Unit
mW
mA
_ C
_ C
V
V
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
any voltage higher than maximum rated volt-
ages to this high–impedance circuit. For proper
operation, V in and V out should be constrained
to the range V SS
appropriate logic voltage level (e.g., either V SS
or V DD ). Unused outputs must be left open.
This device contains protection circuitry to
Unused inputs must always be tied to an
T A = – 55 to 125 C for all packages.
INHIBIT
CLOCK
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
MC14522B
MC14526B
V SS
Q3
PE
Q0
P3
P0
PIN ASSIGNMENT
1
2
3
4
5
6
7
8
v
MC14522B MC14526B
(V in or V out )
16
15
14
13
12
10
11
9
DW SUFFIX
CASE 751G
CERAMIC
CASE 620
CASE 648
L SUFFIX
P SUFFIX
Q2
V DD
P2
CF
“0”
P1
RESET
Q1
PLASTIC
Plastic
Ceramic
SOIC
SOIC
v
V DD .
1