CY7C007-20JC Cypress Semiconductor Corporation., CY7C007-20JC Datasheet
CY7C007-20JC
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CY7C007-20JC Summary of contents
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... Features • True Dual-Ported memory cells which allow simulta- neous access of the same memory location • 32K x 8 organization (CY7C007) • 32K x 9 organization (CY7C017) • 0.35-micron CMOS for optimum speed/power [1] • High-speed access: 12 /15/20 ns • Low operating power — Active: I ...
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... Functional Description The CY7C007 and CY7C017 are low-power CMOS 32K x 8/9 dual-port static RAMs. Various arbitration schemes are includ the devices to handle situations when multiple proces- sors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory ...
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... Power Ground No Connect Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage .......................................... >2001V Latch-Up Current .................................................... >200 mA Operating Range Range Commercial Industrial Shaded areas contain advance information. 3 CY7C007 CY7C017 CY7C007 CY7C007 CY7C017 CY7C017 -15 - 190 180 50 45 0.05 0.05 Description –I/O for x8 devices and I/O – ...
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... Com’l. 125 205 Indust. Com’l. 0.05 0.5 Indust. Com’l. 115 185 Indust. [6] Test Conditions MHz 5. CY7C007 CY7C017 CY7C007 CY7C017 -15 -20 Typ. Max. Min. Typ. Max. 2.4 0.4 0.4 2.2 0.8 0.8 10 –10 10 190 280 180 275 215 305 ...
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... Note: 8. Test Conditions pF. PRELIMINARY R = 250 TH OUTPUT (b) Thévenin Equivalent (Load 1) [8] 3.0V GND 1. Capacitance (pF) (b) Load Derating Curve 5 CY7C007 CY7C017 893 OUTPUT 347 = 1.4V (c) Three-State Delay (Load 2) (Used for & HZWE including scope and jig) ALL INPUT PULSES 90% 90% 10% 10 ...
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... For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. 15. Test conditions used are Load 2. PRELIMINARY [9] [1] –12 Min. Max less than t and t HZCE LZCE 6 CY7C007 CY7C017 CY7C007 CY7C017 –15 –20 Min. Max. Min. Max ...
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... SEM Address Access Time SAA Data Retention Mode The CY7C007 and CY7C017 are designed with battery back mind. Data retention voltage and supply current are guar- anteed over temperature. The following rules ensure data re- tention: 1. Chip enable (CE) must be held HIGH during data retention, with- ...
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... Read Cycle No. 3 (Either Port) ADDRESS CE DATA OUT Notes: 21. Address valid prior to or coincident with CE transition LOW. 22. To access RAM SEM = access semaphore PRELIMINARY [18, 21, 22] t ACE t DOE t LZOE t LZCE LZCE t ABE t ACE t LZCE , SEM = CY7C007 CY7C017 t HZCE t HZOE DATA VALID OHA t HZCE ...
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... If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state. PRELIMINARY [23, 24, 25, 26 [26] t PWE [28] t HZWE t SD [23, 24, 25, 30 SCE LOW CE or SEM PWE HZWE 9 CY7C007 CY7C017 [28] t HZOE LZWE NOTE allow the I/O drivers to turn off and data to be placed PWE ...
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... SPS PRELIMINARY [31 SCE SOP t SD DATA VALID PWE t SWRD t SOP WRITE CYCLE READ CYCLE [32, 33, 34] MATCH t SPS MATCH = CE = HIGH CY7C007 CY7C017 OHA VALID ADRESS t ACE DATA VALID OUT t DOE ...
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... Switching Waveforms (continued) Timing Diagram of Read with BUSY (M/S=HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Write Timing with Busy Input (M/S=LOW) R/W BUSY Note: 35 LOW PRELIMINARY [35 MATCH t PWE t SD VALID MATCH t BLA t PWE CY7C007 CY7C017 BHA t BDD t DDD VALID t WDD ...
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... Note: 36 violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted. PS PRELIMINARY [36] ADDRESS MATCH BLC ADDRESS MATCH BLC [36 ADDRESS MISMATCH t t BLA BHA ADDRESS MISMATCH t t BLA BHA 12 CY7C007 CY7C017 t BHC t BHC ...
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... OE L INT L Notes: 37. t depends on which enable pin ( depends on which enable pin (CE or R/W INS INR L PRELIMINARY t WC WRITE 7FFF [37 [38] t INR t WC WRITE 7FFE [37 [38] t INR ) is deasserted first asserted last CY7C007 CY7C017 t RC READ 7FFF t RC READ 7FFE ...
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... Architecture The CY7C007 and CY7C017 consist of an array of 32K words of 8 and 9 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins per- mit independent access for reads or writes to any location in memory. To handle simultaneous writes/reads to the same location, a BUSY pin is provided on each port ...
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... No change. Left port has no write access to semaphore 0 1 Left port obtains semaphore token 1 1 Semaphore free 1 0 Right port has semaphore token 1 1 Semaphore free 0 1 Left port has semaphore token 1 1 Semaphore free 15 CY7C007 CY7C017 Operation Right Port 0R–14R 7FFF L ...
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... Ordering Information 32K x8 Asynchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 12 CY7C007-12JC 15 CY7C007-15JC CY7C007-15JI 20 CY7C007-20JC CY7C007-20JI Shaded areas contain advance information. 32K x9 Asynchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 12 CY7C017-12JC 15 CY7C017-15JC CY7C017-15JI 20 CY7C017-20JC CY7C017-20JI Shaded areas contain advance information. Document #: 38–00673–B ...
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... POR circuit is at fault. Applicable devices—All speed/package/temperature combi- nations of the following: • CY7C007 • CY7C017 Cypress design change—Cypress design team has identified the root cause. A permanent circuit change and die revision will be available beginning in October and will be identified by the letter “ ...