CY7C408A-25DMB Cypress Semiconductor Corporation., CY7C408A-25DMB Datasheet

no-image

CY7C408A-25DMB

Manufacturer Part Number
CY7C408A-25DMB
Description
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C408A-25DMB
Manufacturer:
CY
Quantity:
4 805
Part Number:
CY7C408A-25DMB
Manufacturer:
CY
Quantity:
650
Part Number:
CY7C408A-25DMB
Manufacturer:
CYP
Quantity:
558
Part Number:
CY7C408A-25DMB 5962-8966402XA
Manufacturer:
CY
Quantity:
15
Features
Functional Description
The CY7C408A and CY7C409A are 64-word deep by 8- or
9-bit wide first-in first-out (FIFO) buffer memories. In addition
to the industry-standard handshaking signals, almost full/al-
most empty (AFE) and half-full (HF) flags are provided.
AFE is HIGH when the FIFO is almost full or almost empty,
otherwise AFE is LOW. HF is HIGH when the FIFO is half full,
otherwise HF is LOW.
The CY7C408A has an output enable (OE) function.
The memory accepts 8- or 9-bit parallel words as its inputs (DI
– DI
ready (IR) control signal is HIGH. The data is output, in the
Logic Block Diagram
Cypress Semiconductor Corporation
• 64 x 8 and 64 x 9 first-in first-out (FIFO) buffer memory
• 35-MHz shift in and shift out rates
• Almost Full/Almost Empty and Half Full flags
• Dual-port RAM architecture
• Fast (50-ns) bubble-through
• Independent asynchronous inputs and outputs
• Output enable (CY7C408A)
• Expandable in word width and FIFO depth
• 5V
• TTL complete
• Capable of withstanding greater than 2001V electro-
• 300-mil, 28-pin DIP
static discharge voltage
8
) under the control of the shift in (SI) input when the input
(7C409A) DI 8
HF
10% supply
H
H
L
L
DI 7
DI 0
MR
SI
IR
.
.
.
CONTROL
DATA IN
MASTER
LOGIC
RESET
INPUT
Flag Definitions
AFE
H
H
L
L
WRITEMULTIPLEXER
READ MULTIPLEXER
WRITE POINTER
READ POINTER
MEMORY
ARRAY
Words Stored
32 - 55
56 - 64
9 - 31
0 - 8
3901 North First Street
ALMOST EMPTY
ALMOST FULL/
HALF FULL
DATAOUT
CONTROL
OUTPUT
LOGIC
0
same order as it was stored on the DO
under the control of the shift out (SO) input when the output
ready (OR) control signal is HIGH. If the FIFO is full (IR LOW),
pulses at the SI input are ignored; if the FIFO is empty (OR
LOW), pulses at the SO input are ignored.
The IR and OR signals are also used to connect the FIFOs in
parallel to make a wider word or in series to make a deeper
buffer, or both.
Parallel expansion for wider words is implemented by logically
ANDing the IR an OR outputs (respectively) of the individual
FIFOs together ( Figure 5 ). The AND operation insures that all
of the FIFOs are either ready to accept more data (IR HIGH)
or ready to output data (OR HIGH) and thus compensate for
variations in propagation delay times between devices.
Serial expansion (cascading) for deeper buffer memories is
accomplished by connecting data outputs of the FIFO closet
to the data source (upstream device) to the data inputs of the
following (downstream) FIFO ( Figure 4 ). In addition, to insure
proper operation, the SO signal of the upstream FIFO must be
connected to the OR output of the upstream FIFO. In this serial
expansion configuration, the IR and OR signals are used to
pass data through the FIFOs.
Reading and writing operations are completely asynchronous,
allowing the FIFO to be used as a buffer between two digital
machines of widely differing operating frequencies. The high
shift in and shift out rates of these FIFOs, and their throughput
rate due to the fast bubblethrough time, which is due to their
dual-port RAM architecture, make them ideal for high-speed
communications and controllers.
C408A–1
AFE
HF
DO 0
DO 7
DO 8 (7C409A)
OE (7C408A)
OR
SO
San Jose
.
.
.
64 x 8 Cascadable FIFO
64 x 9 Cascadable FIFO
(7C408A) NC
(7C409A) DI 8
GND
DI 0
DI 1
DI 2
DI 4
DI 3
DI 5
Pin Configurations
GND
DI 0
DI 1
DI 2
DI 3
DI 4
DI 5
DI 6
DI 7
AFE
HF
IR
SI
5
6
7
8
9
10
11
CA 95134
12 13 14 15
July 1986 – Revised July 1994
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
3 2 1
7C408A
7C409A
7C408A
7C409A
28
1617 18
28
27
26
25
24
23
22
21
20
19
18
17
16
15
27
0
CY7C408A
CY7C409A
26
– DO
25
24
23
22
21
20
19
V CC
MR
SO
OR
DO 0
DO 1
GND
DO 2
DO 3
DO 4
DO 5
DO 6
DO 7
OE (7C408A)
DO 8 (7C409A)
C408A–2
C408A–3
OR
DO 0
DO 1
GND
DO 2
DO 3
DO 4
408-943-2600
8
output pins

Related parts for CY7C408A-25DMB

CY7C408A-25DMB Summary of contents

Page 1

... Capable of withstanding greater than 2001V electro- static discharge voltage • 300-mil, 28-pin DIP Functional Description The CY7C408A and CY7C409A are 64-word deep 9-bit wide first-in first-out (FIFO) buffer memories. In addition to the industry-standard handshaking signals, almost full/al- most empty (AFE) and half-full (HF) flags are provided. ...

Page 2

... mA/MHz CC CCQ Test Conditions MHz 4. 482 5V 3.0V R2 GND 5 pF 256 INCLUDING JIG AND SCOPE (b) C408A–4 C408A–6 2 CY7C408A CY7C409A 7C408A-25 7C408A-35 7C409A-25 7C409A-35 25 125 150 Ambient Temperature + +125 C [3] Min. Max. 2.4 2.2 3.0 10 Commercial Military ( )/ Max ALL INPUT PULSES ...

Page 3

... Test Conditions Min. Note 7 Note 7 23 Note 7 25 Note 8 0 Note 8 30 Note 7 23 Note Note 9 5 Note 9 30 Note 10 6 Note 11 6 Note 12 Note Note conditions exist. BT required). required). 3 CY7C408A CY7C409A 7C408A-25 7C408A-35 7C409A-25 7C409A-35 Max. Min. Max. Min. Max ...

Page 4

... SHIFT OUT t PHSO OUTPUT READY t HSO DATA OUT HF (LOW) AFE Notes: 14. FIFO contains 8 words. 15. FIFO contains 9 words. I/f O NOTE 14 t PLSI t DLIR I/f I/f O NOTE 15 t PLSO t DLOR t DHAFE 4 CY7C408A CY7C409A I DHIR t DLAFE O t DHOR t SOR t OD C408A–7 C408A–8 ...

Page 5

... DATA IN t SSI AFE (LOW) HF Data Out Timing Diagram SHIFT OUT t PHSO OUTPUT READY t HSO DATA OUT HF AFE (LOW) Output Enable (CY7C408A only) OUTPUT ENABLE DATA OUT Notes: 16. FIFO contains 31 words. 17. FIFO contains 32 words. I/f O NOTE 16 t PLSI t DLIR t I/f I/f O ...

Page 6

... INPUT READY DATA IN Notes: 18. FIFO contains 55 words. 19. FIFO contains 56 words. 20. FIFO contains 64 words. I/f O NOTE 18 t PLSI t DLIR t I/f I/f O NOTE 19 t PLSO t DLOR t DLAFE SIR 6 CY7C408A CY7C409A I DHIR DHAFE O t DHOR t SOR PIR t HIR C408A–12 C408A–13 C408A–14 ...

Page 7

... Fall-Through, Data In to Data Out Diagram SHIFT IN NOTE 21 SHIFT OUT OUTPUT READY DATA OUT Master Reset Timing Diagram MASTER RESET INPUT READY OUTPUT READY SHIFT IN DATA OUT HF AFE Notes: 21. FIFO is empty SOR t PMR t DIR t DOR t DSI t LZMR AFE 7 CY7C408A CY7C409A t POR C408A–15 C408A–16 ...

Page 8

... The conventional definitions of fall-through and bubble-back do not apply to the CY7C408A and CY7C409A FIFOs be- cause the data is not physically propagated through the mem- ory. The read and write pointers are incremented instead of moving the data ...

Page 9

... MHz and then the entire packet may be shifted out MHz Figure 2. Shifting Words Out UPSTREAM DOWNSTREAM 128 x 9 Configuration HF/AFE CY7C408A CY7C409A [28] [29] are transmitted, this phenomenon does EMPTY C408A– OUTX N C408A–19 OR OUTPUT READY SO SHIFT OUT DATA OUT C408A–20 [22,23,24,25,26] . ...

Page 10

... Transmission of data packets assumes that up to the maximum cumulative capacity of the FIFOs is shifted in without simultaneous shift out clock occurring. The complement of this holds when data is shifted out as a packet. 192 x 27 Configuration [23,24,25,26,27] 10 CY7C408A CY7C409A HF/AFE SHIFT OUT COMPOSITE OUTPUT READY C408A– ...

Page 11

... Figure 6 applies with f ) for two different interchanged. SOx 400 350 f =30MHz SIx 300 250 200 150 f =35MHz SIx 100 OUTPUT RATE BOTTOM FIFO (MHz) SOx 11 CY7C408A CY7C409A can be sustained when reading data pack- SOx [31] If data is SIx C408A–22 and f SOx ...

Page 12

... AMBIENT TEMPERATURE ( C) NORMALIZED I vs. FREQUENCY 1.1 1.0 0.9 0.8 0.7 0.0 400 600 800 1000 CY7C408A CY7C409A OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE =5. = 125 0.0 1.0 2.0 3.0 OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE ...

Page 13

... Ordering Information Frequency (MHz) Ordering Code 15 CY7C408A-15PC CY7C408A-15VC CY7C408A-15DMB CY7C408A-15LMB 25 CY7C408A-25PC CY7C408A-25VC CY7C408A-25DMB CY7C408A-25LMB 35 CY7C408A-35PC CY7C408A-35VC Frequency (MHz) Ordering Code 15 CY7C409A-15PC CY7C409A-15VC CY7C409A-15DMB CY7C409A-15LMB 25 CY7C409A-25PC CY7C409A-25VC CY7C409A-25DMB CY7C409A-25LMB 35 CY7C409A-35PC CY7C409A-35VC Package Name Package Type P21 28-Lead (300-Mil) Molded DIP V21 28-Lead (300-Mil) Molded SOJ ...

Page 14

... SIR 10, 11 HIR 10, 11 PIR 10, 11 POR 10, 11 SIIR 10, 11 SOOR 10, 11 DLZOE 10, 11 DHZOE 10, 11 DHHF 10, 11 DLHF 10, 11 DLAFE 10, 11 DHAFE 10 10 10, 11 PMR 10, 11 DSI 10, 11 DOR 10, 11 DIR 10, 11 LZMR 10, 11 AFE 10 Document #: 38-00059-G 14 CY7C408A CY7C409A ...

Page 15

... Package Diagrams 28-Lead (300-Mil) CerDIP D22 MIL-STD-1835 D-15 Config.A 28-Square Leadless Chip Carrier L64 28-Lead (300-Mil) Molded DIP P21 15 CY7C408A CY7C409A MIL-STD-1835 C-4 ...

Page 16

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 28-Lead (300-Mil) Molded SOJ V21 CY7C408A CY7C409A ...

Related keywords