CY7B9514V-AC Cypress Semiconductor Corporation., CY7B9514V-AC Datasheet
CY7B9514V-AC
Specifications of CY7B9514V-AC
Available stocks
Related parts for CY7B9514V-AC
CY7B9514V-AC Summary of contents
Page 1
... CY7B9514V • 3901 North First Street • San Jose CY7B9514V 81 FC0+ 79 FC0– CD0 77 AVSS_P4 TOUT0– 75 TOUT0+ EAVCC_TX0 73 AVCC_P4 TCLK+ 71 TCLK– EAVCC_TCLK 69 TSER3– TSER3+ PWR_DWN 67 TSER2– 65 TSER2+ AVCC_TX TSER1– 63 TSER1+ 61 AVSS_TX FC_TX+ FC_TX– 59 MODE1 TSER0– ...
Page 2
... RSER1– LFI1 TSER1+ TSER1– Channel 1 RCLK2+ RCLK2– PLL RSER2+ RSER2– LFI2 TSER2+ TSER2– Channel 2 RCLK3+ RCLK3– PLL RSER3+ RSER3– LFI3 TSER3+ TSER3– Channel 3 REFOUT PLL TCLK+ x8 TCLK– Control & Test 7B9514V-2 2 CY7B9514V ...
Page 3
... Quad UNI Processor Ref Clk Igt WAC-413 Output to VNS 67200 MUX Logic or 4 UNI Processor PMC-Sierra PM5345 IgT WAC-013 Rockwell BT8222 3 CY7B9514V Receive ParallelData ReceiveStart of Cell Read Strobe Address Cell Transmit P arallel Data Transmit S tart of Cell Read Strobe Cell Packet Reassembly ...
Page 4
... LOOP3 (TSER±) is used by the Receive PLL for clock and data recovery. PRELIMINARY CC or left unconnected, the entire Receive PLL will be powered down. CC and TSER leaving them both unconnected CY7B9514V and RIN– leaving them both uncon leaving them both unconnected. ...
Page 5
... DC supply. EAVCC_RX2 EAVCC_RX3 PRELIMINARY ) the PLLs operate at the SONET STS-1 line rate of 51.84 MHz. The SS /2, the TSER± inputs substitute for the internal PLL CC ). When the MODE1 input is left floating or held CY7B9514V ). The transition detector is CC /2, CC ...
Page 6
... The absence of data transitions can be caused by a broken transmission media, a broken transmitter problem with the transmit or receive media coupling. The CY7B9514V will detect a quiet link by counting the number of 6 CY7B9514V ...
Page 7
... RS_SER_DATA± and RS_SER_CLK± inputs of the WAC-413 device as shown in Figure addition, the CY7B9514V provides transmit data output buffering for direct drive of cable transmission media. The CY7B9514V has two local reference clock inputs. An in- ternal mux controls which input clock is used as the reference ...
Page 8
... Latch-Up Current .....................................................>200 mA PRELIMINARY Zo=50 Zo=50 Figure 2. Termination Network Design Termination Network V CC Zo=50 470 pF 50 Zo=50 50 Power Down Control (CYBUS3384) Operating Range Range Commercial +150 C Industrial +125 C 0.5V to +5.0V + 0.5 CY7B9514V Termination Network V CC 470 PWR_DWN Ambient Temperature + +85 C 3.3V 10% 10% ...
Page 9
... TSER/RIN ILE(MIN) CD TSER/RIN CD TSER/RIN TSER/RIN Test Load= – > 0°C PWR_DWN = PECLOUT pins are LOW forced Test Conditions MHz / left floating) the CY7B9514V Min. Max. 2 0.5 0.8 –50 +50 50 +50 2.4 0.45 +0.5 +300 –250 +250 +0.5 +300 250 +250 V 1.145 1.475 CC 1 ...
Page 10
... Cypress uses constant current (ATE) load configurations and forcing functions. This figure is for reference only. h PRELIMINARY [5] (b) PECL AC Test Load V IHE 2.0V 1.0V 20% V ILE < < 7B9514V-5 (d) PECL Input Test Waveform 10 CY7B9514V < (Includes fixture and probe capacitance) 7B9514V-7 [5] V IHE 80% 80% 20% ...
Page 11
... Switching Waveforms t RPWL REFCLK TSER t PD TOUT PRELIMINARY Description MODE0=LOW MODE0=HIGH MODE0=LOW MODE0=HIGH [4] MODE0=LOW MODE0=HIGH [4] [4] [7] MODE0=LOW MODE0=HIGH [8] signals cross). t RPWH 7B9514V–9 11 CY7B9514V Min. Max. Unit 6.41 6.55 MHz 19.24 19.64 MHz 19.50 19.10 ns 6.50 6.40 ns 200 ps 200 0.4 1.2 ns 3000 s ...
Page 12
... Switching Waveforms (continued) t ODC RCLK+ RSER RIN Ordering Information Package Ordering Code Name CY7B9514V-AC A101 Document #: 38-00648-D PRELIMINARY t ODC / / Package Type 100-Lead ( mm) Molded TQFP 12 CY7B9514V t DH 7B9514V–10 7B9514V–11 OperatingRange Commercial ...
Page 13
... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY CY7B9514V 51-85050-A ...