CY7B9911V-7JC Cypress Semiconductor Corporation., CY7B9911V-7JC Datasheet
CY7B9911V-7JC
Specifications of CY7B9911V-7JC
Related parts for CY7B9911V-7JC
CY7B9911V-7JC Summary of contents
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... Document Number: 38-07408 Rev. *D High Speed Low Voltage Programmable Skew Functional Description The CY7B9911V 3.3V RoboClock+™ High Speed Low Voltage Programmable Skew Clock Buffer (LVPSCB) offers user selectable control over system clock functions. These multiple output clock drivers provide the system integrator with functions necessary to optimize the timing of high perfor- mance computer systems ...
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... GND 12 22 GND Description Table 1. “Test Mode” on page 4 under the Table 2. Table 2. Table 2. Table 2. CY7B9911V 3.3V RoboClock+™ 2F0 GND 1F1 1F0 V CCN 1Q0 1Q1 GND GND Table 2. Table 2. Table 2. Table 2. “Block Diagram Description” on page 3. Page [+] Feedback ...
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... LOW indicates a connection to GND, and MID indicates an open connection. Internal termination the V and Time Unit Generator (see). Nominal frequency (f NOM CO Table / NOM has reached 2.8V. CC CY7B9911V 3.3V RoboClock+™ Table 2 shows the nine possible output [1] Output Functions 1Q0, 1Q1, 3Q0, 3Q1 4Q0, 4Q1 3F0, 4F0 2Q0, 2Q1 – ...
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... INVERT Test Mode The TEST input is a three level input. In normal system operation, this pin is connected to ground, allowing the CY7B9911V to operate as described in Description” on page 3. For testing purposes, any of the three level inputs can have a removable jumper to ground or be tied LOW through a 100W resistor. This enables an external tester to change the state of these pins ...
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... Figure 2 shows the LVPSCB configured as a zero skew clock buffer. In this mode the CY7B9911V is used as the basis for a low skew clock distribution tree. When all the function select inputs (xF0, xF1) are left open, each of the outputs are aligned and drive a terminated transmission line to an independent load ...
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... LVPSCB to multiply the clock rate at the REF input by either two or four. This mode enables the designer to distribute a low frequency clock between various portions of the system, and then locally multiply the clock rate to a more suitable CY7B9911V 3.3V RoboClock+™ ⁄ ⁄ ...
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... TEST Figure 8 shows the CY7B9911V connected in series to construct a zero skew clock distribution tree between boards. Delays of the downstream clock buffers are programmed to compensate for the wire length (that is, select negative skew equal to the wire delay) necessary to connect them to the master clock source, approximating a zero delay clock tree. Cascaded clock buffers accumulates low frequency jitter because of the non-ideal filtering characteristics of the PLL filter ...
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... CY7B9911V must be tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only. 8. Total output current per output pair is approximated by the following expression that includes device current plus load current: CY7B9911V: ICCN = [(4 + 0.11F) + [[((835 – ...
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... RMS [12] Peak-to-Peak CY7B9911V 3.3V RoboClock+™ [10] Max Unit 10 pF 3.0V 2.0V V =1.5V th 0.8V ≤1ns CY7B9911V-5 Unit Min Typ Max 15 30 MHz 110 5.0 ns 5.0 ns See Table 1 0.1 0.25 ns 0.25 0.5 ns 0.6 0.7 ns 0.5 1 ...
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... JR Jitter Notes 11. Test measurement levels for the CY7B9911V are TTL levels (1.5V to 1.5V). Test conditions assume signal transition times less and output loading as shown in the AC Test Loads and Waveforms 12. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters. ...
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... AC Timing Diagrams REF OTHER Q INVERTED Q REF DIVIDED BY 2 REF DIVIDED BY 4 Document Number: 38-07408 Rev REF RPWL t RPWH t ODCV t ODCV t t SKEWPR, SKEWPR SKEW0,1 SKEW0,1 t SKEW2 t SKEW3,4 t SKEW3,4 t SKEW1,3, 4 CY7B9911V 3.3V RoboClock+™ SKEW2 t SKEW3,4 t SKEW2,4 Page [+] Feedback ...
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... Ordering Information Accuracy (ps) Ordering Code 500 CY7B9911V-5JC 500 CY7B9911V-5JCT [23] 700 CY7B9911V-7JC [23] 700 CY7B9911V-7JCT Pb-Free 500 CY7B9911V-5JXC 500 CY7B9911V-5JXCT [23] 700 CY7B9911V-7JXC [23] 700 CY7B9911V-7JXCT Note 23. Parts not recommended for the new design. Document Number: 38-07408 Rev. *D Package Type 32-Pb Plastic Leaded Chip Carrier 32-Pb Plastic Leaded Chip Carrier – ...
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... Package Diagram Figure 10. 32-Pin Plastic Leaded Chip Carrier J65 Document Number: 38-07408 Rev. *D CY7B9911V 3.3V RoboClock+™ 51-85002-*B Page [+] Feedback ...
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... Document History Page Document Title: CY7B9911V 3.3V RoboClock+™ High Speed Low Voltage Programmable Skew Clock Buffer Document Number: 38-07408 Orig. of REV. ECN NO. Issue Date Change ** 114350 3/20/02 *A 299713 See ECN *B 404630 See ECN *C 1199925 See ECN KVM/AESA Added Note 23: Parts not recommended for the new design in Ordering ...