CY7B993V-2AI Cypress Semiconductor Corporation., CY7B993V-2AI Datasheet
CY7B993V-2AI
Specifications of CY7B993V-2AI
Related parts for CY7B993V-2AI
CY7B993V-2AI Summary of contents
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... Cypress Semiconductor Corporation Document #: 38-07127 Rev. *F High-speed Multi-phase PLL Clock Buffer Functional Description The CY7B993V and CY7B994V High-speed Multi-phase PLL Clock Buffers offer user-selectable control over system clock functions. This multiple-output clock driver provides the system integrator with functions necessary to optimize the timing of high-performance computer and communication systems ...
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... GND 17 2DS1 18 1DS1 19 VCCQ 20 4DS0 21 3DS0 22 2DS0 23 1DS0 24 GND Document #: 38-07127 Rev. *F 100-pin TQFP CY7B993/ RoboClock CY7B993V CY7B994V VCCQ 74 REFA+ 73 REFA – 72 REFSEL 71 REFB– 70 REFB+ 69 2F0 GND 66 2QA0 65 VCCN 64 2QA1 63 GND 62 GND 61 2QB0 60 VCCN 59 2QB1 58 GND 57 FBF0 56 1F0 55 GND ...
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... DIS1 VCCN VCCN GND (3_level) VCCN 3QA0 3QA1 GND 3QB0 Pin Description , LOW indicates a connection to GND, and MID indicates an open connection. Internal termination CC RoboClock CY7B993V CY7B994V 9 10 FBKA– FBKA+ FBSEL REFA+ GND REFA– VCCN REFB+ VCCN 2QA0 1F0 ...
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... These two blocks, along with the VCO, form a PLL that tracks the incoming REF signal. The CY7B993V/994V have a flexible REF and FB input scheme. These inputs allow the use of either differential LVPECL or single-ended LVTTL inputs. To configure as single-ended LVTTL inputs, the complementary pin must be left open (internally pulled to 1 ...
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... REF. For example, if the output used for feedback is programmed to shift –8t forward in time skew will effectively be skewed 16t ) of the V and Phase Generator. f NOM CO when the output connected undivided. NOM RoboClock CY7B993V CY7B994V Output Skew Function Feed- back Bank1 Bank2 Bank3 Bank4 Bank –4t –4t – ...
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... When a bank of outputs is disabled to HI-Z state, the respective bank of outputs will go HI-Z immediately. Table 5. DIS[1:4]/FBDIS Pin Functionality OUTPUT_MODE DIS[1:4]/FBDIS HIGH/LOW LOW HIGH HIGH LOW HIGH MID X CY7B993V CY7B994V Output Mode ENABLED HI-Z HOLD-OFF FACTORY TEST Page [+] Feedback ...
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... MHz is 16 (with 25-pF load and 0-m/s air flow). Typical Safe Operating Zone (25-pF Load, 0-m /s air flow ) 100 Safe Operating Zone Num ber of Outputs at 185 MHz Figure 2. Typical Safe Operating Zone CY7B993V CY7B994V 16 18 Page [+] Feedback ...
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... Min mA Min. < Min. < GND Max Max Min. < Min. < Min. < GND IN RoboClock CY7B993V CY7B994V Ambient Temperature V CC ° ° 3.3V ± 10 +70 C ° ° 3.3V ± 10% – +85 C Min. Max. Unit = –30 mA 2.4 – Min. 2.4 – – 0 Min. – 0 µ ...
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... MHz for CY7B993V, f NOM at maximum frequency and maximum CCN RoboClock CY7B993V CY7B994V Min. Max. Unit – 250 mA – 250 mA – – ...
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... OUTPUT 200 MHz (a) LVTTL AC Test Load 3.3V 2.0V 0.8V GND < (b) TTL Input Test Waveform = 185 MHz 200 MHz. L RoboClock CY7B993V CY7B994V CY7B993/4V-5 Typ. Max. Min. Typ. Max. Unit – 500 – – 700 ps – 200 – ...
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... SKEW2 INVERTED Q Ordering Information Propagation Max. Speed Delay (ps) (MHz) Ordering Code 250 100 CY7B993V-2AC 250 100 CY7B993V-2ACT 250 100 CY7B993V-2AI 250 100 CY7B993V-2AIT 250 200 CY7B994V-2AC 250 200 CY7B994V-2ACT 250 200 CY7B994V-2BBC 250 200 CY7B994V-2BBCT 250 200 CY7B994V-2AI 250 200 CY7B994V-2AIT ...
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... CY7B994V-2BBXCT 100-ball Thin Ball Grid Array - Tape and Reel 250 200 CY7B994V-2AXI 250 200 CY7B994V-2AXIT 250 200 CY7B994V-2BBXI 250 200 CY7B994V-2BBXIT 500 100 CY7B993V-5AXC 500 100 CY7B993V-5AXCT 500 100 CY7B993V-5AXI 500 100 CY7B993V-5AXIT 500 200 CY7B994V-5AXC 500 200 CY7B994V-5AXCT 500 200 CY7B994V-5BBXC 500 200 ...
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... Package Diagrams 100-pin Thin Plastic Quad Flat Pack (TQFP) A100 Document #: 38-07127 Rev. *F RoboClock CY7B993V CY7B994V 51-85048-*B Page [+] Feedback ...
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... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. RoboClock CY7B993V CY7B994V 51-85107-*B Page ...
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... Added three industrial packages HWT Added TTB Features RBI Power-up requirements to operating conditions information RGL Added min. F value of 12 MHz for CY7B993V and 24 MHz for CY7B994V out to switching characteristics table Corrected prop delay limit parameter from (t Output Description paragraph RGL Added clock input frequency (f ...