CY7B995AI Cypress Semiconductor Corporation., CY7B995AI Datasheet

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CY7B995AI

Manufacturer Part Number
CY7B995AI
Description
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

Specifications of CY7B995AI

Case
QFP-44L
Features
Cypress Semiconductor Corporation
Document #: 38-07337 Rev. *D
2.5V or 3.3V operation
Split output bank power supplies
Output frequency range: 6 MHz to 200 MHz
45 ps typical cycle-cycle jitter
± 2% max output duty cycle
Selectable output drive strength
Selectable positive or negative edge synchronization
Eight LVTTL outputs driving 50 Ω terminated lines
LVCMOS/LVTTL over-voltage tolerant reference input
Selectable phase-locked loop (PLL) frequency range and lock
indicator
Phase adjustments in 625/1250 ps steps up to ± 7.5 ns
(1-6, 8, 10, 12) x multiply and (1/2,1/4)x divide ratios
Spread-Spectrum compatible
Power down mode
Selectable reference divider
Industrial temperature range: –40°C to +85°C
44-pin TQFP package
Logic Block Diagram
PD#/DIV
DS1:0
2F1:0
3F1:0
4F1:0
1F1:0
REF
FB
198 Champion Court
3
3
/N
/R
3
2.5/3.3V 200-MHz High-Speed
Description
The CY7B995 RoboClock
eight-output, 200 MHz clock driver. It features output phase
programmability which is necessary to optimize the timing of high
performance computer and communication systems.
The user can program both the frequency and the phase of the
output banks through nF[0:1] and DS[0:1] pins. The adjustable
phase feature allows the user to skew the outputs to lead or lag
the reference clock. Any one of the outputs can be connected to
feedback to achieve different reference frequency multiplication,
and divide ratios and zero input-output delay.
The device also features split output bank power supplies, which
enable the user to run two banks (1Qn and 2Qn) at a power
supply level, different from that of the other two banks (3Qn and
4Qn). The three-level PE/HD pin also controls the synchroni-
zation of the output signals to either the rising, or the falling edge
of the reference clock and selects the drive strength of the output
buffers. The high drive option (PE/HD = MID) increases the
output current from ± 12 mA to ± 24 mA.
TEST
Multi-Phase PLL Clock Buffer
3
3
3
3
3
3
3
3
3
Phase
PLL
Select
PE/HD
and /K
and /M
Phase
Select
Phase
Select
Phase
Select
3
San Jose
FS
3
VDDQ4
VDDQ1
sOE#
,
CA 95134-1709
RoboClock
®
VDDQ3
1Q0
1Q1
2Q0
2Q1
3Q0
3Q1
4Q0
4Q1
LOCK
is a low voltage, low power,
Revised September 27, 2007
®
, CY7B995
408-943-2600
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CY7B995AI Summary of contents

Page 1

Features ■ 2.5V or 3.3V operation ■ Split output bank power supplies ■ Output frequency range: 6 MHz to 200 MHz ■ typical cycle-cycle jitter ■ ± 2% max output duty cycle ■ Selectable output drive strength ■ ...

Page 2

Pinouts Figure 1. Pin Diagram - 44 Pin TQFP Package Top view PD#/DIV PE/HD VDDQ4 VDDQ4 Document #: 38-07337 Rev 4F1 1 sOE CY7B995 ...

Page 3

Table 1. Pin Definitions - 44 Pin TQFP Package [1] Pin Name IO 39 REF I LVTTL/LVCMOS LVTTL 37 TEST I 3-Level 2 sOE LVTTL 4 PE/ 3-Level 34, 33, 36, 35, nF[1:0] ...

Page 4

Table 3. Feedback Divider Settings DS[1:0] N-Feedback Input Permitted Output Divider Divider Connected addition to the reference and feedback ...

Page 5

In addition to determining whether the outputs synchronize to the rising or the falling edge of the reference signal, the 3-level PE/HD pin controls the output buffer drive strength as indicated in Table 10 on page 5. Refer to the ...

Page 6

DC Specifications at 2.5V Parameter Description V 2.5 Operating Voltage DD V Input LOW Voltage IL V Input HIGH Voltage IH [11] V Input HIGH Voltage IHH [11] V Input MID Voltage IMM [11] V Input LOW Voltage ILL ...

Page 7

DC Specifications at 3.3V Parameter Description V 3.3 Operating Voltage DD V Input LOW Voltage IL V Input HIGH Voltage IH [11] V Input HIGH Voltage IHH [11] V Input MID Voltage IMM [11] V Input LOW Voltage ILL I ...

Page 8

Switching Characteristics Parameter Description F Output frequency range OR VCO VCO Lock Range LR VCO VCO Loop Bandwidth LBW [13] t Matched-Pair Skew SKEWPR [13] t Output-Output Skew SKEW0 t SKEW1 t SKEW2 t SKEW3 [13] t Output-Output Skew SKEW4 ...

Page 9

AC Timing Definitions t PWH REF OTHER Q INVERTED Q DIVIDE BY 2 OUTPUT DIVIDE BY 4 OUTPUT With PE HIGH (LOW), the REF rising (falling) edges are aligned to the FB rising (falling) edges. Also, ...

Page 10

AC Test Loads and Waveforms Figure 3. For Lock Output and all other Outputs Figure 4. 3.3V LVTTL and 2.5V LVTTL Output Waveforms t ...

Page 11

... Ordering Information Part Number CY7B995AC 44 TQFP CY7B995ACT 44 TQFP – Tape and Reel CY7B995AI 44 TQFP CY7B995AIT 44 TQFP – Tape and Reel Pb-free CY7B995AXC 44 TQFP CY7B995AXCT 44 TQFP – Tape and Reel CY7B995AXI 44 TQFP CY7B995AXIT 44 TQFP – Tape and Reel Document #: 38-07337 Rev. *D Package Type Product Flow Commercial, 0° ...

Page 12

Package Drawing and Dimension Figure 6. 44-Pb Thin Plastic Quad Flat Pack ( 1.0 mm) A44SB Document #: 38-07337 Rev. *D ® RoboClock , CY7B995 51-85155*A Page [+] Feedback [+] Feedback ...

Page 13

Document History Page Document Title: CY7B995 Roboclock Document Number: 38-07337 REV. ECN No. Issue Date Change ** 122626 01/10/03 *A 205743 See ECN *B 362760 See ECN *C 389237 See ECN *D 1562063 See ECN PYG/AESA Added Status column to ...

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