CY7C007AV-25JC Cypress Semiconductor Corporation., CY7C007AV-25JC Datasheet

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CY7C007AV-25JC

Manufacturer Part Number
CY7C007AV-25JC
Description
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

Specifications of CY7C007AV-25JC

Case
PLCC-68L

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C007AV-25JC
Manufacturer:
CY
Quantity:
11
Part Number:
CY7C007AV-25JC
Manufacturer:
CYP
Quantity:
117
Cypress Semiconductor Corporation
Document #: 38-06051 Rev. *C
CY7C138AV CY7C139AV CY7C144AV CY7C145AV CY7C006AV CY7C016AV CY7C007AV CY7C017AV 3.3V 4K/8K/16K/32K x 8/9
Dual-Port Static RAM
Features
Logic Block Diagram
• True Dual-Ported memory cells which allow
• 4K/8K/16K/32K x 8 organizations
• 4K/8K/16K/32K x 9 organizations
• 0.35-micron CMOS for optimum speed/power
• High-speed access: 20/25 ns
• Low operating power
• Fully asynchronous operation
For the most recent information, visit the Cypress web site at www.cypress.com
Notes:
1. I/O
2. A
3. BUSY is an output in master mode and an input in slave mode.
A
A
CE
OE
R/W
SEM
BUSY
INT
R/W
CE
OE
I/O
simultaneous access of the same memory location
(CY7C0138AV/144AV/006AV/007AV)
(CY7C0139AV/145AV/016AV/017AV)
— Active: I
— Standby: I
0L
0L
L
0L
L
L
–A
–A
0
L
L
–A
L
0
L
L
–I/O
–I/O
[2]
[2]
L
11–14L
11–14L
11
[3]
for 4K devices; A
7
7/8L
for x8 devices; I/O
[1]
CC
SB3
= 115 mA (typical)
= 10 µA (typical)
12–15
0
8/9
–A
0
12
–I/O
for 8K devices; A
8
Address
for x9 devices.
Decode
12–15
0
–A
13
3901 North First Street
for 16K devices; A
Control
I/O
True Dual-Ported
Semaphore
RAM Array
Arbitration
Interrupt
M/S
0
–A
14
for 32K devices;
• Automatic power-down
• Expandable data bus to 16/18 bits or more using Master/
• On-chip arbitration logic
• Semaphores included to permit software handshaking
• INT flag for port-to-port communication
• Pin select for Master or Slave
• Commercial and Industrial Temperature Ranges
• Available in 68-pin PLCC (all) and 64-pin TQFP
• Pb-Free packages available
Slave chip select when using more than one device
between ports
(7C006AV & 7C144AV)
Control
I/O
3.3V 4K/8K/16K/32K x 8/9
San Jose
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
Dual-Port Static RAM
Address
Decode
12–15
CA 95134
CY7C007AV/017AV
12–15
8/9
Revised June 6, 2005
I/O
A
A
408-943-2600
0R
0R
0R
[3]
–A
–A
–I/O
BUSY
11–14R
11–14R
SEM
[2]
[2]
R/W
R/W
[1]
INT
OE
CE
CE
OE
7/8R
R
R
R
R
R
R
R
R
R
[+] Feedback

Related parts for CY7C007AV-25JC

CY7C007AV-25JC Summary of contents

Page 1

... CY7C138AV CY7C139AV CY7C144AV CY7C145AV CY7C006AV CY7C016AV CY7C007AV CY7C017AV 3.3V 4K/8K/16K/32K x 8/9 Dual-Port Static RAM Features • True Dual-Ported memory cells which allow simultaneous access of the same memory location • 4K/8K/16K/32K x 8 organizations (CY7C0138AV/144AV/006AV/007AV) • 4K/8K/16K/32K x 9 organizations (CY7C0139AV/145AV/016AV/017AV) • 0.35-micron CMOS for optimum speed/power • ...

Page 2

... CY7C145AV. 8R Document #: 38-06051 Rev. *C 68-Pin PLCC Top View CY7C138AV ( CY7C139AV ( 2728 29 30 3132 68-Pin PLCC Top View CY7C144AV ( CY7C145AV ( 2728 29 30 3132 CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV INT 54 L BUSY 53 L GND 52 51 M/S BUSY INT INT L BUSY L GND M/S BUSY R INT ...

Page 3

... I/O 4L I/O 5L GND I GND I/O 0R I I/O 3R I/O 4R I/O 5R I/O6 R Notes: 8. I/O for CY7C016AV and CY7C017AV only. NC for other parts. 9. Address line for CY7C007AV and CY7C017AV only. NC for other parts. Document #: 38-06051 Rev. *C 64-Pin TQFP Top View CY7C144AV ( ...

Page 4

... Typical Standby Current for I (µA) SB3 (Both Ports CMOS level) Document #: 38-06051 Rev. *C 64-Pin TQFP Top View CY7C006AV (16K CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV -20 20 120 35 10 µA CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV INT L BUSY L GND M/S BUSY R INT CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV -25 25 115 30 10 µA Page [+] Feedback ...

Page 5

... CY7C138AV/9AV, 1FFE for the CY7C144AV/5AV, 3FFE for the CY7C006AV/16AV, 7FFE for the CY7C007AV/17AV) is the mailbox for the left port. When one port writes to the other port’s mailbox, an interrupt is generated to the owner. The interrupt is reset when the owner reads the contents of the mailbox ...

Page 6

... If both ports attempt to access the semaphore within t memory locations. definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore. CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV before attempting to SOP represents the 0–2 is used zero each other, the semaphore will ...

Page 7

... OUT Notes: 10. The Voltage on any input or I/O pin can not exceed the power pin during power-up. 11. Pulse width < 20 ns. 12. Industrial parts are available in CY7C007AV and CY7C017AV only. 13 1/t . All inputs cycling 1/t (except output enable means no address or control lines change. This applies only to inputs at CMOS level ...

Page 8

... CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV -20 Min less than t and t is less than t HZCE LZCE HZOE CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV 3. 590Ω OUTPUT 435Ω (c) Three-State Delay (Load 2) (Used for & HZWE LZWE including scope and jig) -25 Max. Min. Max. Unit ...

Page 9

... BDD WDD 23 GND 25°C. This parameter is guaranteed but not tested Document #: 38-06051 Rev. *C [15] (continued) CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV -20 Min Timing and reaches the Parameter CC ICC DR1 –t (actual –t (actual). PWE DDD SD CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV -25 Max. Min. Max. Unit ...

Page 10

... Address valid prior to or coincident with CE transition LOW. 28. To access RAM SEM = access semaphore Document #: 38-06051 Rev. *C [24, 25, 26 DATA VALID [24, 27, 28] t ACE t DOE t LZOE t LZCE LZCE t ABE t ACE t LZCE , SEM = CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV t OHA t HZCE t HZOE DATA VALID OHA t HZCE Page [+] Feedback ...

Page 11

... If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state. Document #: 38-06051 Rev. *C [29, 30, 31, 32 [32] t PWE [33] t HZWE t SD [29, 30, 31, 36 SCE LOW CE or SEM PWE CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV [33] t HZOE LZWE Note allow the I/O drivers to turn off and data HZWE SD Page [+] Feedback ...

Page 12

... SPS Document #: 38-06051 Rev. *C [37] t SAA VALID ADRESS SCE SOP t SD DATA VALID PWE t SWRD t SOP WRITE CYCLE READ CYCLE [38, 39, 40] MATCH t SPS MATCH = CE = HIGH CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV t OHA t ACE DATA VALID OUT t DOE Page [+] Feedback ...

Page 13

... Timing Diagram of Read with BUSY (M/S=HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Write Timing with Busy Input (M/S=LOW) R/W BUSY Note: 41 LOW Document #: 38-06051 Rev. *C CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV [41 MATCH t PWE t SD VALID MATCH t BLA t WDD t PWE CY7C007AV/017AV BHA t BDD t DDD VALID Page [+] Feedback ...

Page 14

... BUSY will be asserted. PS Document #: 38-06051 Rev. *C [42] ADDRESS MATCH BLC ADDRESS MATCH BLC [42 ADDRESS MISMATCH t t BLA BHA ADDRESS MISMATCH t t BLA BHA CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV t BHC t BHC Page [+] Feedback ...

Page 15

... R 44 depends on which enable pin (CE INS INR L Document #: 38-06051 Rev [43 (See Functional Description) [44] t INR t WC [43 (See Functional Description) [44] t INR ) is deasserted first R asserted last. L CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV t RC READ FFF t RC READ FFE Page [+] Feedback ...

Page 16

... No change. Left port has no write access to semaphore 0 1 Left port obtains semaphore token 1 1 Semaphore free 1 0 Right port has semaphore token 1 1 Semaphore free 0 1 Left port has semaphore token 1 1 Semaphore free CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV Operation Right Port INT 0R–14R [45 FFF H [45] ...

Page 17

... Thin Quad Flat Pack J81 68-Pin Plastic Leaded Chip Carrier A65 64-Pin Thin Quad Flat Pack A65 64-Pin Pb-Free Thin Quad Flat Pack J81 68-Pin Plastic Leaded Chip Carrier CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV 64-Pin TQFP X X Operating Range Commercial Commercial Operating Range Commercial ...

Page 18

... Plastic Leaded Chip Carrier J81 68-Pin Plastic Leaded Chip Carrier Package Name Package Type J81 68-Pin Plastic Leaded Chip Carrier J81 68-Pin Plastic Leaded Chip Carrier J81 68-Pin Plastic Leaded Chip Carrier CY7C007AV/017AV Operating Range Commercial Commercial Operating Range Commercial Industrial Commercial Operating Range ...

Page 19

... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 68-Lead Plastic Leaded Chip Carrier J81 CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV 51-85046-*B 51-85005-*A Page [+] Feedback ...

Page 20

... Document History Page Document Title: CY7C138AV/144AV/006AV/CY7C139AV/145AV/016AV/CY7C007AV/017AV 3.3V 4K/8K/16K/32K x 8/9 Dual Port SRAM Document Number: 38-06051 Issue Orig. of REV. ECN NO. Date Change ** 110203 12/02/01 SZV *A 122301 12/27/02 *B 237623 See ECN YDT *C 373615 See ECN PCX Document #: 38-06051 Rev. *C Description of Change Change from Spec number: 38-00837 to 38-06051 ...

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