CY7C008-12AC Cypress Semiconductor Corporation., CY7C008-12AC Datasheet
CY7C008-12AC
Specifications of CY7C008-12AC
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CY7C008-12AC Summary of contents
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... CY7C018/01964K/128K x 8/9 Dual-Port Static RAM Features • True Dual-Ported memory cells that allow simultaneous access of the same memory location • 64K x 8 organization (CY7C008) • 128K x 8 organization (CY7C009) • 64K x 9 organization (CY7C018) • 128K x 9 organization (CY7C019) • 0.35-micron CMOS for optimum speed/power [1] • ...
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... Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by a chip select (CE) pin. The CY7C008/009 and CY7C018/019 are available in 100-pin Thin Quad Plastic Flatpack (TQFP) packages. 100-Pin TQFP (Top View) 97 ...
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... CY7C019 (128K x 9) CY7C018 (64K CY7C008/009 CY7C018/019 [1] -12 12 195 55 0.05 CY7C008/009 CY7C018/019 A7R 72 A8R 71 A9R 70 A10R 69 A11R 68 A12R 67 A13R 66 A14R 65 A15R 64 A16R 63 GND CE0R 57 CE1R 56 SEMR 55 R/WR 54 OER 53 GND 52 GND CY7C008/009 CY7C008/009 CY7C018/019 CY7C018/019 -15 - 190 180 50 45 0.05 0.05 [6] Unit Page ...
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... Ground No Connect Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage........................................... >1100V Latch-Up Current .................................................... >200 mA ° ° +150 C Operating Range ° ° +125 C Range Commercial Industrial CY7C008/009 CY7C018/019 Description < V and CE > –A for 128K devices –I/O for x8 devices and I/O – ...
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... Ind. [10] Description Test Conditions ° MHz 5.0V CC (except output enable means no address or control lines change. This applies only to inputs at CMOS level CY7C008/009 CY7C018/019 CY7C008/009 CY7C018/019 -15 -20 Min. Typ. Max. Min. Typ. 2.4 2.4 0.4 2.2 2.2 0.8 –10 10 –10 ...
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... ALL INPUT PULSES 3.0V 90% 10% GND ≤ [12] 1.00 0.90 0.80 0.70 = 1.4V 0.60 TH 0.50 0.40 0.30 0.20 0.10 0. CY7C008/009 CY7C018/019 OUTPUT VTH = 1.4V (c) Three-State Delay (Load 2) (Used for including scope and jig) 90% 10% ≤ Capacitance (pF) (b) Load Derating Curve 893Ω 347Ω ...
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... For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. Document #: 38-06041 Rev. *D [13] CY7C008/009 CY7C018/019 [1] -12 -15 Min. Max. Min. Max less than t and t is less than t HZCE LZCE HZOE LZOE CY7C008/009 CY7C018/019 -20 Min. Max. Unit time. SCE . Page ...
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... SEM Address Access Time SAA Data Retention Mode The CY7C008/009 and CY7C018/019 are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: 1. Chip Enable (CE) must be held HIGH during data retention, ...
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... To access RAM SEM = access semaphore Document #: 38-06041 Rev. *D [22, 23, 24 [22, 25, 26] t ACE t DOE t LZOE t LZCE LZCE t ABE t ACE t LZCE . This waveform cannot be used for semaphore reads. , SEM = CY7C008/009 CY7C018/019 t OHA DATA VALID t HZCE t HZOE DATA VALID OHA t HZCE Page ...
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... HZWE t SD [27, 28, 29, 34 SCE LOW CE or SEM. PWE . HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be SD CY7C008/009 CY7C018/019 [32] t HZOE LZWE NOTE allow the I/O drivers to turn off and data ...
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... SPS Document #: 38-06041 Rev. *D [35 SCE t SD DATA VALID PWE t SWRD t SOP WRITE CYCLE [36, 37, 38] MATCH t SPS MATCH = CE = HIGH CY7C008/009 CY7C018/019 t t SAA OHA VALID ADRESS t ACE t SOP DATA VALID OUT t DOE READ CYCLE Page ...
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... Timing Diagram of Read with BUSY (M/S=HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Write Timing with Busy Input (M/S=LOW) R/W BUSY Note: 39 LOW Document #: 38-06041 Rev. *D [39 MATCH t PWE t SD VALID MATCH t BLA t PWE CY7C008/009 CY7C018/019 BHA t BDD t DDD VALID t WDD Page ...
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... BUSY will be asserted. PS Document #: 38-06041 Rev. *D [40] ADDRESS MATCH BLC ADDRESS MATCH BLC [40 ADDRESS MATCH ADDRESS MISMATCH t t BLA BHA ADDRESS MATCH ADDRESS MISMATCH t t BLA BHA CY7C008/009 CY7C018/019 t BHC t BHC Page ...
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... R 42 depends on which enable pin (CE INS INR Document #: 38-06041 Rev [41 [42] [42] t INR t WC [41 [42] [42] t INR ) is deasserted first R asserted last CY7C008/009 CY7C018/019 t RC READ FFFF (1FFFF for CY7C009/19 READ FFFE (1FFFE for CY7C009/19) Page ...
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... Architecture The CY7C008/009 and CY7C018/019 consist of an array of 64K and 128K words of 8 and 9 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins permit independent access for reads or writes to any location in memory. To handle simultaneous writes/reads to the same location, a BUSY pin is provided on each port ...
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... No change. Left port has no write access to semaphore 0 1 Left port obtains semaphore token 1 1 Semaphore free 1 0 Right port has semaphore token 1 1 Semaphore free 0 1 Left port has semaphore token 1 1 Semaphore free CY7C008/009 CY7C018/019 Operation [43] Right Port R 0R–16R ...
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... Ordering Information 64K x8 Asynchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 12 CY7C008-12AC 15 CY7C008-15AC CY7C008-15AXC 20 CY7C008-20AC 128K x 8 Asynchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 12 CY7C009-12AC 15 CY7C009-15AC CY7C009-15AXC 20 CY7C009-20AC CY7C009-20AI 64K x 9 Asynchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 12 CY7C018-12AC 15 CY7C018-15AC 20 CY7C018-20AC 128K x 9 Asynchronous Dual-Port SRAM ...
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... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C008/009 CY7C018/019 ...
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... Document History Page Document Title: CY7C008/009, CY7C018/019 64K/128K x 8/9 Dual Port Static RAM Document Number: 38-06041 Issue REV. ECN NO. Date ** 110189 09/29/01 *A 113542 04/15/02 *B 122291 12/27/02 *C 236764 SEE ECN *D 393436 See ECN Document #: 38-06041 Rev. *D Orig. of Change Description of Change SZV Change from Spec number: 38-00665 to 38-06041 OOR Change pin 85 from BUSYL to BUSYR (pg ...