CY7C016A-20AC Cypress Semiconductor Corporation., CY7C016A-20AC Datasheet
CY7C016A-20AC
Specifications of CY7C016A-20AC
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CY7C016A-20AC Summary of contents
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... True dual-ported memory cells which allow simultaneous access of the same memory location • 16K x 8 organization (CY7C006A) • 32K x 8 organization (CY7C007A) • 16K x 9 organization (CY7C016A) • 32K x 9 organization (CY7C017A) • 0.35-micron CMOS for optimum speed/power [1] • High-speed access: 12 /15/20 ns • ...
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... This pin is I/O for CY7C017A only connect pin for 16K devices. 14 Document #: 38-06045 Rev. *D 68-Pin PLCC Top View CY7C006A (16K CY7C007A (32K CY7C017A (32K 80-Pin TQFP Top View CY7C007A (32K x 8) CY7C016A (16K X 9) CY7C006A/CY7C007A CY7C016A/CY7C017A INT L 53 BUSY L GND 52 M/S ...
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... Ports CMOS Level) SB3 Document #: 38-06045 Rev. *D 64-Pin TQFP Top View CY7C006A (16K CY7C006A CY7C007A CY7C016A CY7C017A [1] -12 12 195 55 0.05 CY7C006A/CY7C007A CY7C016A/CY7C017A INT L BUSY L GND M/S BUSY R INT CY7C006A CY7C006A CY7C007A CY7C007A CY7C016A CY7C016A CY7C017A CY7C017A -15 - 190 180 50 45 0.05 0.05 Page [+] Feedback ...
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... Chip Select (CE) pin. The CY7C006A, CY7C007A, and CY7C017A are available in 68-pin PLCC packages, the CY7C006A is also available in 64-pin TQFP, and the CY7C007A and CY7C016A are also available in 80-pin TQFP packages. Write Operation Data must be set up for a duration R/W in order to guarantee a valid write ...
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... The operation of the interrupts and their interaction with Busy are summarized in Table 2. Busy The CY7C006A, CY7C007A, CY7C016A and CY7C017A provide on-chip arbitration to resolve simultaneous memory location access (contention). If both ports’ CEs are asserted and an address match occurs within t ...
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... Ind. Com’l. 125 205 Ind. Com’l. 0.05 0.5 Ind. Com’l. 115 185 L Ind. Test Conditions ° MHz 5.0V CC CY7C006A/CY7C007A CY7C016A/CY7C017A [8] .........................................–0.5V to +7.0V Ambient Temperature V CC ° ° 5V ± 10 +70 C -15 -20 Typ. Max. Min. Typ. Max. Unit 2.4 V 0.4 ...
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... TH OUTPUT 1.4V TH (b) Thévenin Equivalent (Load 1) [11] 3.0V 10% GND ≤ Capacitance (pF) (b) Load Derating Curve CY7C006A/CY7C007A CY7C016A/CY7C017A 893Ω OUTPUT 347Ω (c) Three-State Delay (Load 2) (Used for & HZWE LZWE including scope and jig) ALL INPUT PULSES 90% 90% 10% ≤ ...
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... For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. 18. Test conditions used are Load 2. 19. For 15 ns industrial parts t Min. is 0.5 ns. HD Document #: 38-06045 Rev. *D CY7C006A/CY7C007A CY7C016A/CY7C017A [12] CY7C006A CY7C007A CY7C016A CY7C017A [1] –12 –15 Min. Max. Min. Max ...
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... SEM Address Access Time SAA Data Retention Mode The CY7C006A, CY7C007A, CY7C016A, and CY7C017A are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: 1. Chip Enable (CE) must be held HIGH during data retention, ...
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... DATA OUT Notes: 25. Address valid prior to or coincident with CE transition LOW. 26. To access RAM SEM = access semaphore Document #: 38-06045 Rev. *D [22, 25, 26] t ACE t DOE t LZOE t LZCE LZCE t ABE t ACE t LZCE , SEM = CY7C006A/CY7C007A CY7C016A/CY7C017A t HZCE t HZOE DATA VALID OHA t HZCE Page [+] Feedback ...
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... If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state. Document #: 38-06045 Rev. *D [27, 28, 29, 30 [30] t PWE [32] t HZWE t SD [27, 28, 29, 34 SCE LOW CE or SEM PWE CY7C006A/CY7C007A CY7C016A/CY7C017A [32] t HZOE LZWE NOTE allow the I/O drivers to turn off and data HZWE SD Page [+] Feedback ...
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... SPS Document #: 38-06045 Rev. *D [35 VALID ADRESS SCE SOP t SD DATA VALID PWE t SWRD t SOP WRITE CYCLE READ CYCLE [36, 37, 38] MATCH t SPS MATCH = CE = HIGH CY7C006A/CY7C007A CY7C016A/CY7C017A t OHA t ACE DATA VALID OUT t DOE Page [+] Feedback ...
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... Timing Diagram of Read with BUSY (M/S=HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Write Timing with Busy Input (M/S=LOW) R/W BUSY Note: 39 LOW Document #: 38-06045 Rev. *D [39 MATCH t PWE t SD VALID MATCH t BLA t WDD t PWE CY7C006A/CY7C007A CY7C016A/CY7C017A BHA t BDD t DDD VALID Page [+] Feedback ...
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... BUSY will be asserted. PS Document #: 38-06045 Rev. *D [40] ADDRESS MATCH BLC ADDRESS MATCH BLC [40 ADDRESS MISMATCH t t BLA BHA ADDRESS MISMATCH t t BLA BHA CY7C006A/CY7C007A CY7C016A/CY7C017A t BHC t BHC Page [+] Feedback ...
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... INT L Notes: 41. t depends on which enable pin ( depends on which enable pin (CE INS INR L Document #: 38-06045 Rev WRITE 7FFF [41 [42] t INR t WC WRITE 7FFE [41 [42] t INR ) is deasserted first R asserted last. L CY7C006A/CY7C007A CY7C016A/CY7C017A t RC READ 7FFF t RC READ 7FFE Page [+] Feedback ...
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... No change. Left port has no write access to semaphore 0 1 Left port obtains semaphore token 1 1 Semaphore free 1 0 Right port has semaphore token 1 1 Semaphore free 0 1 Left port has semaphore token 1 1 Semaphore free CY7C006A/CY7C007A CY7C016A/CY7C017A Operation Right Port INT R R 0R–14R R [44 [43 7FFF ...
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... CY7C007A-15AC CY7C007A-15JC 20 CY7C007A-20AC CY7C007A-20JC CY7C007A-20JXC 16K x9 Asynchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 12 CY7C016A-12AC 15 CY7C016A-15AC CY7C016A-15AXC 20 CY7C016A-20AC 32K x9 Asynchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 12 CY7C017A-12JC 15 CY7C017A-15JC 20 CY7C017A-20JC Document #: 38-06045 Rev. *D Package Name Package Type A65 64-Pin Thin Quad Flat Pack ...
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... Package Diagrams 64-Lead Thin Plastic Quad Flat Pack ( 1.4 mm) A65 64-Lead Pb-Free Thin Plastic Quad Flat Pack ( 1.4 mm) A65 Document #: 38-06045 Rev. *D CY7C006A/CY7C007A CY7C016A/CY7C017A 51-85046-*B Page [+] Feedback ...
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... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 80-Pin Thin Plastic Quad Flat Pack A80 CY7C006A/CY7C007A CY7C016A/CY7C017A 51-85065-*B 51-85005-*A Page ...
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... Document History Page Document Title: CY7C006A/CY7C007A/CY7C016A/CY7C017A 32K/16K x 8, 32K/16K x 9 Dual Port Static RAM Document Number: 38-06045 Issue Orig. of REV. ECN NO. Date Change ** 110197 09/29/01 SZV *A 122295 12/27/02 RBI *B 237620 See ECN YDT *C 345376 See ECN AEQ *D 387333 See ECN PCX Document #: 38-06045 Rev ...