CY7C018V-15AC Cypress Semiconductor Corporation., CY7C018V-15AC Datasheet
CY7C018V-15AC
Specifications of CY7C018V-15AC
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CY7C018V-15AC Summary of contents
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... Commercial and Industrial Temperature Ranges • Available in 100-pin TQFP • Pb-Free packages available I/O I/O Control Control True Dual-Ported RAM Array Interrupt Semaphore Arbitration M/S • 198 Champion Court • San Jose CY7C008V/009V CY7C018V/019V 3.3V 64K/128K x 8/9 Dual-Port Static RAM R 8/9 [1] I/O –I/O 0R 7/8R ...
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... The CY7C008V/009V and CY7018V/019V are available in and dual-port 100-pin Thin Quad Plastic Flatpacks (TQFP). 100-Pin TQFP (Top View CY7C009V (128K x 8) CY7C008V (64K CY7C008V/009V CY7C018V/019V A7R 72 A8R 71 A9R 70 A10R 69 A11R 68 A12R 67 A13R 66 A14R 65 A15R 64 A16R ...
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... Selection Guide Maximum Access Time Typical Operating Current Typical Standby Current for I SB1 (Both ports TTL level) Typical Standby Current for I SB3 (Both ports CMOS level) Note: 5. This pin is NC for CY7C018V. Document #: 38-06044 Rev. *C 100-Pin TQFP (Top View CY7C019V (128K x 9) ...
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... Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage........................................... >1100V ° ° Latch-Up Current .................................................... >200 +150 C Operating Range ° ° +125 C Range Commercial +0.5V CC Industrial CY7C008V/009V CY7C018V/019V Description ≤ V ≥ V and –A for 128K devices –I/O for x8 devices and I/O –I/O 0 ...
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... OUTPUT (b) Thévenin Equivalent (Load 1) ALL INPUT PULSES 3.0V 90% 10% GND ≤ (except output enable). f=0 means no address or control lines change. This applies only to inputs at CMOS level CY7C008V/009V CY7C018V/019V CY7C008V/009V CY7C018V/019V -20 -25 2.4 2.4 0.4 0.4 2.2 2.2 0.8 0.8 5 –5 5 – ...
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... For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. 16. Test conditions used are Load 1. Document #: 38-06044 Rev. *C [10] CY7C008V/009V CY7C018V/019V -15 -20 Min. Max. Min. Max less than t and t is less than t HZCE LZCE HZOE LZOE CY7C008V/009V CY7C018V/019V -25 Min. Max. Unit time. SCE . Page ...
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... Document #: 38-06044 Rev. *C [10] (continued) -15 Min. Max Timing after V reaches the CC Parameter ICC DR1 –t (actual –t (actual). WDD PWE DDD SD CY7C008V/009V CY7C018V/019V CY7C008V/009V CY7C018V/019V -20 -25 Min. Max. Min. Max Data Retention Mode 3.0V 3.0V > 2. – 0. [18] Test Conditions Max. ...
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... To access RAM SEM = access semaphore Document #: 38-06044 Rev. *C [19, 20, 21 [19, 22, 23] t ACE t DOE t LZOE t LZCE LZCE t ABE t ACE t LZCE . This waveform cannot be used for semaphore reads. , SEM = CY7C008V/009V CY7C018V/019V t OHA DATA VALID t HZCE t HZOE DATA VALID OHA t HZCE Page ...
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... HZWE t SD [24, 25, 26, 31 SCE LOW CE or SEM. PWE . HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be SD CY7C008V/009V CY7C018V/019V [29] t HZOE LZWE NOTE allow the I/O drivers to turn off and data PWE ...
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... SPS Document #: 38-06044 Rev. *C [32 SCE t SD DATA VALID PWE t SWRD t SOP WRITE CYCLE [33, 34, 35] MATCH t SPS MATCH = CE = HIGH CY7C008V/009V CY7C018V/019V t t SAA OHA VALID ADRESS t ACE t SOP DATA VALID OUT t DOE READ CYCLE Page ...
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... Timing Diagram of Read with BUSY (M/S=HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Write Timing with Busy Input (M/S=LOW) R/W BUSY Note: 36 LOW Document #: 38-06044 Rev. *C [36 MATCH t PWE t SD VALID MATCH t BLA t PWE CY7C008V/009V CY7C018V/019V BHA t BDD t DDD VALID t WDD Page ...
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... BUSY will be asserted. PS Document #: 38-06044 Rev. *C [37] ADDRESS MATCH BLC ADDRESS MATCH BLC [37 ADDRESS MATCH ADDRESS MISMATCH t t BLA BHA ADDRESS MATCH ADDRESS MISMATCH t t BLA BHA CY7C008V/009V CY7C018V/019V t BHC t BHC Page ...
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... R 39 depends on which enable pin (CE INS INR Document #: 38-06044 Rev [38 [39] [39] t INR t WC [38 [39] [39] t INR ) is deasserted first R asserted last CY7C008V/009V CY7C018V/019V t RC READ FFFF (1FFFF for CY7C009V/19V READ 1FFE (1FFFF for CY7C009V/19V) Page ...
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... Table 3 shows sample semaphore operations. When reading a semaphore, all data lines output the semaphore value. The read value is latched in an output CY7C008V/009V CY7C018V/019V of each other, the busy logic will PS is violated, one port PS after an address match or t ...
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... No change. Left port has no write access to semaphore 0 1 Left port obtains semaphore token 1 1 Semaphore free 1 0 Right port has semaphore token 1 1 Semaphore free 0 1 Left port has semaphore token 1 1 Semaphore free CY7C008V/009V CY7C018V/019V Operation [40] Right Port R 0R–16R FFFF (or 1FFFF) ...
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... Ordering Information 64K x8 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code 15 CY7C008V-15AC 20 CY7C008V-20AC 25 CY7C008V-25AC CY7C008V-25AXC 64K x9 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code 15 CY7C018V-15AC 20 CY7C018V-20AC 25 CY7C018V-25AC 128K x8 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code 15 CY7C009V-15AC CY7C009V-15AXC 20 CY7C009V-20AC CY7C009V-20AI CY7C009V-20AXI 25 CY7C009V-25AC CY7C009V-25AXC 128K x9 3.3V Asynchronous Dual-Port SRAM ...
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... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C008V/009V CY7C018V/019V 51-85048-*B Page ...
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... Document History Page Document Title: CY7C008V/009V, CY7C018V/019V 3.3V 64K/128K X 8/9 Dual Port Static RAM Document Number: 38-06044 Issue REV. ECN NO. Date ** 110192 09/29/01 *A 113541 04/15/02 *B 122294 12/27/02 *C 393440 See ECN Document #: 38-06044 Rev. *C Orig. of Change Description of Change SZV Change from Spec number: 38-00669 to 38-06044 OOR Change pin 85 from BUSYL to BUSYR (pg ...