CY7C024AV-20AC Cypress Semiconductor Corporation., CY7C024AV-20AC Datasheet

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CY7C024AV-20AC

Manufacturer Part Number
CY7C024AV-20AC
Description
4K X 16 DUAL-PORT STATIC RAM
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

Specifications of CY7C024AV-20AC

Case
QFP-100L
Cypress Semiconductor Corporation
Document #: 38-06052 Rev. *H
Features
Notes:
1.
2.
3.
4.
• True dual-ported memory cells which allow
• 4/8/16K × 16 organization (CY7C024AV/025AV/026AV)
• 4/8K × 18 organization (CY7C0241AV/0251AV)
• 16K × 18 organization (CY7C036AV)
• 0.35-micron CMOS for optimum speed/power
• High-speed access: 20 and 25 ns
• Low operating power
• Fully asynchronous operation
Logic Block Diagram
simultaneous access of the same memory location
— Active: I
— Standby: I
I/O
I/O
A
BUSY is an output in master mode and an input in slave mode.
0
–A
8
0
R/W
UB
OE
I/O
I/O
A
A
CE
OE
R/W
SEM
BUSY
INT
UB
LB
–I/O
–I/O
CE
LB
11
0L
0L
L
8/9L
0L
L
L
L
L
L
L
for 4K devices; A
–A
–A
L
L
15
7
L
L
L
–I/O
for x16 devices; I/O
for x16 devices; I/O
[3]
11/1213L
[3]
11/12/13L
L
–I/O
[4]
CC
[2]
7/8L
SB3
[1]
15/17L
= 115 mA (typical)
= 10 μA (typical)
0
–A
12/13/14
12
0
9
–I/O
8/9
8/9
for 8K devices; A
–I/O
8
17
for x18 devices.
for x18 devices.
3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM
Address
Decode
12/13/14
0
–A
13
for 16K devices.
3901 North First Street
Control
I/O
True Dual-Ported
Semaphore
RAM Array
Arbitration
Interrupt
M/S
• Automatic power-down
• Expandable data bus to 32/36 bits or more using
• On-chip arbitration logic
• Semaphores included to permit software handshaking
• INT flag for port-to-port communication
• Separate upper-byte and lower-byte control
• Pin select for Master or Slave
• Commercial and industrial temperature ranges
• Available in 100-pin Lead (Pb)-free TQFP and 100-pin
Master/Slave chip select when using more than one
device
between ports
TQFP
Control
I/O
San Jose
CY7C0241AV/0251AV/036AV
CY7C024AV/025AV/026AV
Address
Decode
12/13/14
,
CA 95134
12/13/14
8/9
8/9
Revised June 15, 2005
I/O
A
A
8/9L
0R
0R
408-943-2600
I/O
–A
–A
[4]
–I/O
0L
11/12/13R
11/12/13R
[3]
[3]
–I/O
BUSY
SEM
R/W
15/17R
R/W
[1]
CE
INT
UB
LB
OE
OE
CE
UB
LB
[2]
7/8R
R
R
R
R
R
R
R
R
R
R
R
R
R

Related parts for CY7C024AV-20AC

CY7C024AV-20AC Summary of contents

Page 1

... Dual-Port Static RAM Features • True dual-ported memory cells which allow simultaneous access of the same memory location • 4/8/16K × 16 organization (CY7C024AV/025AV/026AV) • 4/8K × 18 organization (CY7C0241AV/0251AV) • 16K × 18 organization (CY7C036AV) • 0.35-micron CMOS for optimum speed/power • ...

Page 2

... I/O 13L 8 GND 9 I/O 10 14L I/O 11 15L GND Notes the CY7C025AV. 12L the CY7C025AV. 12R Document #: 38-06052 Rev. *H 100-Pin TQFP Top View 100 CY7C024AV (4K × 16) CY7C025AV (8K × 16 CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV INT 65 L BUSY 64 L GND 63 M/S 62 BUSY 61 R INT ...

Page 3

... I/O3R 18 I/O4R 19 I/O5R 20 I/O6R Notes the CY7C0251AV. 12L the CY7C0251AVC. 12R Document #: 38-06052 Rev. *H Top View 100-Pin TQFP CY7C0241AV (4K × 18) CY7C0251AV (8K × 18 CY7C026AV (16K × 16 CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV INT 65 L BUSY 64 L GND 63 M/S 62 BUSY 61 R INT A6L 71 A5L 70 A4L 69 A3L 68 A2L ...

Page 4

... CMOS Level) Document #: 38-06052 Rev. *H 100-Pin TQFP Top View 100 CY7C036AV (16K × 18 CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV -20 20 120 35 10 CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV 13L INT L 65 BUSY 64 L GND 63 M/S 62 BUSY 61 R INT 13R CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV -25 25 115 30 10 Unit μA Page ...

Page 5

... SEM pin must be asserted instead of the CE pin, and communications OE must also be asserted. Interrupts The upper two memory locations may be used for message passing. The highest memory location (FFF for the CY7C024AV/41AV, 1FFF for the CY7C025AV/51AV, 3FFF for CY7C024AV/025AV/026AV –A for 8K devices; A –A for 16K). ...

Page 6

... CY7C026AV/36AV) is the mailbox for the right port and the second-highest memory location (FFE for the CY7C024AV/ 41AV, 1FFE for the CY7C025AV/51AV, 3FFE for the CY7C026AV/36AV) is the mailbox for the left port. When one port writes to the other port’s mailbox, an interrupt is generated to the owner ...

Page 7

... Semaphore-free 1 0 Right port has semaphore token 1 1 Semaphore free 0 1 Left port has semaphore token 1 1 Semaphore-free CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV I/O –I/O Operation 0 8 High Z Deselected: Power-Down High Z Deselected: Power-Down High Z Write to Upper Byte Only Data In Write to Lower Byte Only ...

Page 8

... 3.3V CC (except output enable means no address or control lines change. This applies only to inputs at CMOS level RC CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV [14] ............................... –0. Ambient Temperature 0°C to +70°C [15] –40°C to +85°C CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV -20 -25 Min. Typ. Max. Min. Typ. 2.4 2.4 0.4 2.0 2.0 [16] – ...

Page 9

... C = 30pF (b) Thévenin Equivalent (Load 1) ALL INPUT PULSES 3.0V 90% 90% 10% GND ≤ [19] Description Min. is less than t HZCE LZCE CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV 3.3V OUTPUT 1.4V TH (c) Three-State Delay (Load 2) (Used for HZWE including scope and jig) 10% ≤ CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV -20 -25 Max. Min. Max ...

Page 10

... SEM Address Access Time SAA Data Retention Mode The CY7C024AV/025AV/026AV and CY7C0241AV/0251AV/ 036AV are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: 1. Chip Enable (CE) must be held HIGH during data retention, ...

Page 11

... IL IL Document #: 38-06052 Rev. *H [28, 29, 30 [28, 31, 32] t ACE t DOE t LZOE t LZCE LZCE t ABE t ACE t LZCE and This waveform cannot be used for semaphore reads SEM = access semaphore SEM = CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV t OHA DATA VALID t HZCE t HZOE DATA VALID OHA t HZCE t HZCE . IL Page ...

Page 12

... AW t SCE LOW CE or SEM and a LOW UB or LB. PWE . HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can SEM = SEM = CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV [39] t HZOE LZWE NOTE allow the I/O drivers to turn off and data ...

Page 13

... SPS Document #: 38-06052 Rev. *H [42 SCE t SD DATA VALID PWE t SWRD t SOP WRITE CYCLE [43, 44, 45] MATCH t SPS MATCH = CE = HIGH CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV t t SAA OHA VALID ADRESS t ACE t SOP DATA VALID OUT t DOE READ CYCLE Page ...

Page 14

... Timing Diagram of Read with BUSY (M/S=HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Write Timing with Busy Input (M/S=LOW) R/W BUSY Note: 46 LOW Document #: 38-06052 Rev. *H CY7C0241AV/0251AV/036AV [46 MATCH t PWE t SD VALID MATCH t BLA t PWE CY7C024AV/025AV/026AV BHA t BDD t DDD VALID t WDD Page ...

Page 15

... BUSY will be asserted. PS Document #: 38-06052 Rev. *H [47] ADDRESS MATCH BLC ADDRESS MATCH BLC [47 ADDRESS MATCH ADDRESS MISMATCH t t BLA BHA ADDRESS MATCH ADDRESS MISMATCH t t BLA BHA CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV t BHC t BHC Page ...

Page 16

... Left Side Clears INT : L ADDRESS R INT L Notes: 48. t depends on which enable pin ( 49 depends on which enable pin (CE INS INR Document #: 38-06052 Rev [48 [49] [49] t INR t WC [48 [49] [49] t INR or R deasserted first R asserted last CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV t RC READ 7FFF (OR 1/3FFF READ 7FFE OR 1/3FFE) Page ...

Page 17

... Ordering Information 4K x16 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code 15 CY7C024AV-15AI CY7C024AV-15AXI 20 CY7C024AV-20AC CY7C024AV-20AXC CY7C024AV-20AI CY7C024AV-20AXI 25 CY7C024AV-25AC CY7C024AV-25AXC CY7C024AV-25AI CY7C024AV-25AXI 8K x16 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code 20 CY7C025AV-20AC CY7C025AV-20AXC CY7C025AV-20AXI 25 CY7C025AV-25AC CY7C025AV-25AXC CY7C025AV-25AI CY7C025AV-25AXI 16K x16 3.3V Asynchronous Dual-Port SRAM ...

Page 18

... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV ...

Page 19

... Document History Page Document Title: CY7C024AV/CY7C025AV/CY7C026AV/CY7C0241AV/CY7C0251AV/CY7C036AV 3.3V 4K/8K/16K x 16/18 Dual Port Static RAM Document Number: 38-06052 REV. ECN NO. Issue Date ** 110204 11/11/01 *A 122302 12/27/02 *B 128958 9/03/03 *C 237622 See ECN *D 241968 See ECN *E 276451 See ECN *F 279452 See ECN *G 373580 See ECN ...

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