CY7C0251AV-20AC Cypress Semiconductor Corporation., CY7C0251AV-20AC Datasheet

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CY7C0251AV-20AC

Manufacturer Part Number
CY7C0251AV-20AC
Description
8K X 18 DUAL-PORT STATIC RAM
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

Specifications of CY7C0251AV-20AC

Case
QFP-100L
Cypress Semiconductor Corporation
Document #: 38-06052 Rev. *H
Features
Notes:
1.
2.
3.
4.
• True dual-ported memory cells which allow
• 4/8/16K × 16 organization (CY7C024AV/025AV/026AV)
• 4/8K × 18 organization (CY7C0241AV/0251AV)
• 16K × 18 organization (CY7C036AV)
• 0.35-micron CMOS for optimum speed/power
• High-speed access: 20 and 25 ns
• Low operating power
• Fully asynchronous operation
Logic Block Diagram
simultaneous access of the same memory location
— Active: I
— Standby: I
I/O
I/O
A
BUSY is an output in master mode and an input in slave mode.
0
–A
8
0
R/W
UB
OE
I/O
I/O
A
A
CE
OE
R/W
SEM
BUSY
INT
UB
LB
–I/O
–I/O
CE
LB
11
0L
0L
L
8/9L
0L
L
L
L
L
L
L
for 4K devices; A
–A
–A
L
L
15
7
L
L
L
–I/O
for x16 devices; I/O
for x16 devices; I/O
[3]
11/1213L
[3]
11/12/13L
L
–I/O
[4]
CC
[2]
7/8L
SB3
[1]
15/17L
= 115 mA (typical)
= 10 μA (typical)
0
–A
12/13/14
12
0
9
–I/O
8/9
8/9
for 8K devices; A
–I/O
8
17
for x18 devices.
for x18 devices.
3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM
Address
Decode
12/13/14
0
–A
13
for 16K devices.
3901 North First Street
Control
I/O
True Dual-Ported
Semaphore
RAM Array
Arbitration
Interrupt
M/S
• Automatic power-down
• Expandable data bus to 32/36 bits or more using
• On-chip arbitration logic
• Semaphores included to permit software handshaking
• INT flag for port-to-port communication
• Separate upper-byte and lower-byte control
• Pin select for Master or Slave
• Commercial and industrial temperature ranges
• Available in 100-pin Lead (Pb)-free TQFP and 100-pin
Master/Slave chip select when using more than one
device
between ports
TQFP
Control
I/O
San Jose
CY7C0241AV/0251AV/036AV
CY7C024AV/025AV/026AV
Address
Decode
12/13/14
,
CA 95134
12/13/14
8/9
8/9
Revised June 15, 2005
I/O
A
A
8/9L
0R
0R
408-943-2600
I/O
–A
–A
[4]
–I/O
0L
11/12/13R
11/12/13R
[3]
[3]
–I/O
BUSY
SEM
R/W
15/17R
R/W
[1]
CE
INT
UB
LB
OE
OE
CE
UB
LB
[2]
7/8R
R
R
R
R
R
R
R
R
R
R
R
R
R

Related parts for CY7C0251AV-20AC

CY7C0251AV-20AC Summary of contents

Page 1

Dual-Port Static RAM Features • True dual-ported memory cells which allow simultaneous access of the same memory location • 4/8/16K × 16 organization (CY7C024AV/025AV/026AV) • 4/8K × 18 organization (CY7C0241AV/0251AV) • 16K × 18 organization (CY7C036AV) ...

Page 2

Pin Configurations I/O 10L 5 I/O 6 11L I/O 12L 7 I/O 13L 8 GND 9 I/O 10 14L I/O 11 15L GND I I/O 15 ...

Page 3

... NC 4 I/O10L 5 I/O11L 6 I/O12L 7 I/O13L 8 GND 9 I/O14L 10 I/O15L 11 VCC 12 GND 13 I/O0R 14 I/O1R 15 I/O2R 16 VCC 17 I/O3R 18 I/O4R 19 I/O5R 20 I/O6R Notes the CY7C0251AV. 12L the CY7C0251AVC. 12R Document #: 38-06052 Rev. *H Top View 100-Pin TQFP CY7C0241AV (4K × 18) CY7C0251AV (8K × 18 CY7C026AV (16K × 16 CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV ...

Page 4

Pin Configurations (continued I/O 8L I/O 17L I/O 11L I/O 12L I/O 13L I/O 14L GND I/O 15L I/O 16L V CC GND I/O 0R I I/O 3R I/O 4R I/O 5R I/O ...

Page 5

Pin Definitions Left Port Right Port R/W R –A A –A 0L 13L 0R 13R I/O –I/O I/O –I/O 0L 17L 0R 17R SEM SEM ...

Page 6

CY7C026AV/36AV) is the mailbox for the right port and the second-highest memory location (FFE for the CY7C024AV/ 41AV, 1FFE for the CY7C025AV/51AV, 3FFE for the CY7C026AV/36AV) is the mailbox for the left port. When one port writes to the ...

Page 7

Table 1. Non-Contending Read/Write Inputs CE R ...

Page 8

Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential ............... –0.5V to +4.6V ...

Page 9

AC Test Loads and Waveforms 3. 590Ω OUTPUT 435Ω (a) Normal Load (Load 1) Switching Characteristics Over the Operating Range Parameter Read Cycle t Read Cycle Time RC t Address to Data ...

Page 10

Switching Characteristics Over the Operating Range (continued) Parameter t Data Set-up to Write End SD t Data Hold From Write End HD [22, 23] t R/W LOW to High Z HZWE [22, 23] t R/W HIGH to Low Z LZWE ...

Page 11

Switching Waveforms Read Cycle No. 1 (Either Port Address Access) ADDRESS t OHA DATA OUT PREVIOUS DATA VALID Read Cycle No. 2 (Either Port CE/OE Access) CE and DATA OUT I CC CURRENT I SB [28, ...

Page 12

Switching Waveforms (continued) Write Cycle No. 1: R/W Controlled Timing ADDRESS OE [37, 38 R/W NOTE 40 DATA OUT DATA IN Write Cycle No Controlled Timing ADDRESS [37, 38 R/W DATA IN ...

Page 13

Switching Waveforms (continued) Semaphore Read After Write Timing, Either Side A –A VALID ADRESS 0 2 SEM I R/W OE Timing Diagram of Semaphore Contention A – R/W L SEM L A – ...

Page 14

Switching Waveforms (continued) Timing Diagram of Read with BUSY (M/S=HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Write Timing with Busy Input (M/S=LOW) R/W BUSY Note: 46 LOW. ...

Page 15

Switching Waveforms (continued) Busy Timing Diagram No.1 (CE Arbitration) CE Valid First: L ADDRESS L BUSY R CE Valid First: R ADDRESS L BUSY L Busy Timing Diagram No.2 (Address Arbitration) Left ...

Page 16

Switching Waveforms (continued) Interrupt Timing Diagrams Left Side Sets INT : R ADDRESS WRITE 1FFF (OR 1/3FFF R/W L INT R t INS Right Side Clears INT : R ADDRESS R ...

Page 17

... Asynchronous Dual-Port SRAM Speed (ns) Ordering Code 20 CY7C0241AV-20AC 25 CY7C0241AV-25AC 8K x18 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code 20 CY7C0251AV-20AC 25 CY7C0251AV-25AC Document #: 38-06052 Rev. *H CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV Package Name Package Type A100 100-Pin Thin Quad Flat Pack A100 100-Pin Lead-free Thin Quad Flat Pack ...

Page 18

Asynchronous Dual-Port SRAM Speed (ns) Ordering Code 20 CY7C036AV-20AC 25 CY7C036AV-25AC CY7C036AV-25AXC CY7C036AV-25AI Package Diagram 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100 100-Pin Lead (Pb)-free Thin Plastic Quad Flat Pack (TQFP) A100 All product and company ...

Page 19

... Document History Page Document Title: CY7C024AV/CY7C025AV/CY7C026AV/CY7C0241AV/CY7C0251AV/CY7C036AV 3.3V 4K/8K/16K x 16/18 Dual Port Static RAM Document Number: 38-06052 REV. ECN NO. Issue Date ** 110204 11/11/01 *A 122302 12/27/02 *B 128958 9/03/03 *C 237622 See ECN *D 241968 See ECN *E 276451 See ECN *F 279452 See ECN *G 373580 See ECN ...

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