CY7C027-12AC Cypress Semiconductor Corporation., CY7C027-12AC Datasheet
CY7C027-12AC
Specifications of CY7C027-12AC
Related parts for CY7C027-12AC
CY7C027-12AC Summary of contents
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... CY7C037/03832K/64K x 16/18 Dual-Port Static RAM Features • True Dual-Ported memory cells which allow simulta- neous access of the same memory location • 32K x 16 organization (CY7C027) • 64K x 16 organization (CY7C028) • 32K x 18 organization (CY7C037) • 64K x 18 organization (CY7C038) • 0.35-micron CMOS for optimum speed/power [1] • ...
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... Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by the chip enable pins. The CY7C027/028 and CY7C037/038 are available in 100-pin Thin Quad Plastic Flatpack (TQFP) packages. 100-Pin TQFP (Top View ...
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... CY7C027/028 CY7C037/038 A8R 74 A9R 73 A10R 72 A11R 71 A12R 70 A13R 69 A14R [7] 68 A15R 67 LBR 66 UBR 65 CE0R 64 CE1R 63 SEMR 62 R/WR 61 GND 60 OER 59 GND 58 I/O17R 57 GND 56 I/O16R 55 I/O15R 54 I/O14R 53 I/O13R 52 I/O12R 51 I/O11R CY7C027/028 CY7C037/038 -15 -20 Unit 190 180 0.05 0.05 mA Page [+] Feedback ...
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... Ground No Connect Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage........................................... >1100V Latch-Up Current.................................................... >200 mA ° ° +150 C Operating Range ° ° +125 C Range Commercial [10] Industrial CY7C027/028 CY7C037/038 ≤ V ≥ V and –I/O for x18 –I/O for x18 devices –I/O for x18 devices) ...
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... Ind. Com’l. 125 205 [10] Ind. Com’l. 0.05 0.5 0.05 [10] Ind. Com’l. 115 185 [10] Ind. Test Conditions ° MHz 5.0V CC CY7C027/028 CY7C037/038 -15 -20 Max. Min. Typ. Max. Unit 2.4 V 0.4 0.4 V 2.2 V 0.8 0.8 V µA 10 –10 10 190 280 180 ...
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... Capacitance (pF) (b) Load Derating Curve CY7C027/028 CY7C037/038 893Ω OUTPUT 347Ω (c) Three-State Delay (Load 2) (Used for & t CKLZ OLZ OHZ including scope and jig Page [+] Feedback ...
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... For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. 20. Test conditions used are Load 1. Document #: 38-06042 Rev. *C [14] CY7C027/028 CY7C037/038 [1] -12 -15 Min. Max. Min. Max time. SCE is less than t and t is less than t . HZCE LZCE HZOE LZOE CY7C027/028 CY7C037/038 -20 Min. Max. Unit Page [+] Feedback ...
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... SEM Address Access Time SAA Data Retention Mode The CY7C027/028 and CY7C037/038 are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: 1. Chip enable (CE) must be held HIGH during data retention, ...
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... To access RAM SEM = Document #: 38-06042 Rev. *C [23 ,24, 25 DATA VALID [23, 26, 27] t ACE t DOE t LZOE t LZCE LZCE t ABE t ACE t LZCE . This waveform cannot be used for semaphore reads access semaphore SEM = CY7C027/028 CY7C037/038 t OHA t HZCE t HZOE DATA VALID OHA t HZCE t HZCE Page [+] Feedback ...
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... If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state. Document #: 38-06042 Rev. *C [28, 29, 30, 31 [31] t PWE [34] t HZWE t SD [28, 29, 30, 34, 35 SCE LOW CE or SEM and a LOW PWE . CY7C027/028 CY7C037/038 [34] t HZOE LZWE NOTE allow the I/O drivers to turn off and data HZWE SD Page [+] Feedback ...
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... SPS Document #: 38-06042 Rev. *C [37] t SAA VALID ADRESS SCE SOP t SD DATA VALID PWE t SWRD t SOP WRITE CYCLE READ CYCLE [38, 39, 40] MATCH t SPS MATCH = CE = HIGH CY7C027/028 CY7C037/038 t OHA t ACE DATA VALID OUT t DOE Page [+] Feedback ...
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... Timing Diagram of Read with BUSY (M/S=HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Write Timing with Busy Input (M/S=LOW) R/W BUSY Note: 41 LOW Document #: 38-06042 Rev. *C [41 MATCH t PWE t SD VALID MATCH t BLA t WDD t PWE CY7C027/028 CY7C037/038 BHA t BDD t DDD VALID Page [+] Feedback ...
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... BUSY will be asserted. PS Document #: 38-06042 Rev. *C [42] ADDRESS MATCH BLC ADDRESS MATCH BLC [42 ADDRESS MISMATCH t t BLA BHA ADDRESS MISMATCH t t BLA BHA CY7C027/028 CY7C037/038 t BHC t BHC Page [+] Feedback ...
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... R 44 depends on which enable pin (CE INS INR L Document #: 38-06042 Rev [43 (FFFF for CY7C028/38) [44] t INR t WC [43 (FFFE for CY7C028/38) [44] t INR ) is deasserted first R asserted last. L CY7C027/028 CY7C037/038 t RC READ 7FFF t RC READ 7FFE Page [+] Feedback ...
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... The upper two memory locations may be used for message passing. The highest memory location (7FFF for the CY7C027/37, FFFF for the CY7C028/38) is the mailbox for the right port and the second-highest memory location (7FFE for the CY7C027/37, FFFE for the CY7C028/38) is the mailbox for the left port. When one port writes to the other port’ ...
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... [46 [47] L 7FFE H X CY7C027/028 CY7C037/038 of each other, the SPS Operation 8 Deselected: Power-Down Deselected: Power-Down Write to Upper Byte Only Write to Lower Byte Only Write to Both Bytes Read Upper Byte Only Read Lower Byte Only Read Both Bytes Outputs Disabled Read Data in Semaphore Flag ...
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... Right port obtains semaphore token change. Left port has no write access to semaphore 0 1 Left port obtains semaphore token 1 1 Semaphore free 1 0 Right port has semaphore token 1 1 Semaphore free 0 1 Left port has semaphore token 1 1 Semaphore free CY7C027/028 CY7C037/038 Status Page [+] Feedback ...
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... Ordering Information 32K x16 Asynchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 12 CY7C027-12AC 15 CY7C027-15AC 20 CY7C027-20AC CY7C027-20AXC 64K x16 Asynchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 12 CY7C028-12AC CY7C028-12AXC 15 CY7C028-15AC CY7C028-15AXC CY7C028-15AI CY7C028-15AXI 20 CY7C028-20AC CY7C028-20AI 32K x18 Asynchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 12 ...
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... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C027/028 CY7C037/038 ...
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... Document History Page Document Title: CY7C027/028, CY7C037/038 32K/64K x 16/18 Dual-Port Static RAM Document Number: 38-06042 Issue Orig. of REV. ECN NO. Date Change ** 110190 09/29/01 SZV *A 122292 12/27/02 RBI *B 236765 6/23/04 YDT *C 377454 See ECN PCX Document #: 38-06042 Rev. *C Description of Change Change from Spec number: 38-00666 to 38-06042 ...