CY7C028-20AI Cypress Semiconductor Corporation., CY7C028-20AI Datasheet
CY7C028-20AI
Specifications of CY7C028-20AI
Available stocks
Related parts for CY7C028-20AI
CY7C028-20AI Summary of contents
Page 1
... Features • True Dual-Ported memory cells which allow simulta- neous access of the same memory location • 32K x 16 organization (CY7C027) • 64K x 16 organization (CY7C028) • 32K x 18 organization (CY7C037) • 64K x 18 organization (CY7C038) • 0.35-micron CMOS for optimum speed/power [1] • ...
Page 2
... An automatic power-down feature is controlled independently on each port by the chip enable pins. The CY7C027/028 and CY7C037/038 are available in 100-pin Thin Quad Plastic Flatpack (TQFP) packages. 100-Pin TQFP (Top View CY7C028 (64K x 16) CY7C027 (32K x 16 CY7C027/028 CY7C037/038 80 79 ...
Page 3
Pin Configurations (continued) 100 A9L 1 A10L 2 A11L 3 A12L 4 A13L 5 A14L 6 [7] A15L 7 LBL 8 UBL 9 CE0L 10 CE1L 11 SEML 12 R/WL 13 OEL 14 VCC 15 GND ...
Page 4
... Input Voltage ............................................... –0.5V to +7.0V Notes: 8. The Voltage on any input or I/O pin cannot exceed the power pin during power-up. 9. Pulse width < 20 ns. 10. Industrial parts are available in CY7C028 and CY7C038 only. Document #: 38-06042 Rev. *C Description Chip Enable (CE is LOW when CE 0 Read/Write Enable ...
Page 5
Electrical Characteristics Over the Operating Range Symbol Parameter V Output HIGH Voltage (V = Min –4.0 mA) V Output LOW Voltage (V = Min +4.0 mA) V Input HIGH Voltage IH V ...
Page 6
AC Test Loads and Waveforms 893Ω OUTPUT 347Ω (a) Normal Load (Load 1) 3.0V GND AC Test Loads (Applicable to -12 only 50Ω 50Ω 0 OUTPUT C ...
Page 7
Switching Characteristics Over the Operating Range Parameter Description READ CYCLE t Read Cycle Time RC t Address to Data Valid AA t Output Hold From Address Change OHA [15 LOW to Data Valid ACE t OE LOW to ...
Page 8
Switching Characteristics Over the Operating Range Parameter Description t R/W HIGH after BUSY HIGH (Slave) WH [21] t BUSY HIGH to Data Valid BDD [20] INTERRUPT TIMING t INT Set Time INS t INT Reset Time INR SEMAPHORE TIMING t ...
Page 9
Switching Waveforms Read Cycle No. 1 (Either Port Address Access) ADDRESS OHA DATA OUT PREVIOUS DATA VALID Read Cycle No. 2 (Either Port CE/OE Access) CE and DATA OUT ...
Page 10
Switching Waveforms (continued) Write Cycle No. 1: R/W Controlled Timing ADDRESS OE [32,33 R/W NOTE 35 DATA OUT DATA IN Write Cycle No Controlled Timing ADDRESS [32,33 R/W DATA IN Notes: 28. ...
Page 11
Switching Waveforms (continued) Semaphore Read After Write Timing, Either Side A –A VALID ADRESS SEM I R/W OE Timing Diagram of Semaphore Contention A – R/W L SEM L A –A ...
Page 12
Switching Waveforms (continued) Timing Diagram of Read with BUSY (M/S=HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Write Timing with Busy Input (M/S=LOW) R/W BUSY Note: 41 LOW. ...
Page 13
Switching Waveforms (continued) Busy Timing Diagram No.1 (CE Arbitration) CE Valid First: L ADDRESS L BUSY R CE Valid First: R ADDRESS L BUSY L Busy Timing Diagram No. 2 (Address Arbitration) ...
Page 14
... Switching Waveforms (continued) Interrupt Timing Diagrams Left Side Sets INT : R ADDRESS WRITE 7FFF (FFFF for CY7C028/38 R/W L INT R [44] t INS Right Side Clears INT : R ADDRESS R INT R : Right Side Sets INT L ADDRESS WRITE 7FFE (FFFE for CY7C028/38 R/W R INT L [44] t INS Left Side Clears INT ...
Page 15
... CY7C027/37, FFFF for the CY7C028/38) is the mailbox for the right port and the second-highest memory location (7FFE for the CY7C027/37, FFFE for the CY7C028/38) is the mailbox for the left port. When one port writes to the other port’s mailbox, an interrupt is generated to the owner. The interrupt is reset when the owner reads the contents of the mailbox ...
Page 16
... Flag Reset Left INT Flag Notes: 45. A and A , FFFF/FFFE for the CY7C028/038. 0L–15L 0R–15R 46. If BUSY = L, then no change. R 47. If BUSY = L, then no change. L Document #: 38-06042 Rev. *C access the semaphore within t semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore ...
Page 17
Table 3. Semaphore Operation Example Function I/O –I action Left port writes 0 to semaphore Right port writes 0 to semaphore Left port writes 1 to semaphore Left port writes 0 to semaphore Right port writes 1 to ...
Page 18
... CY7C027-20AC CY7C027-20AXC 64K x16 Asynchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 12 CY7C028-12AC CY7C028-12AXC 15 CY7C028-15AC CY7C028-15AXC CY7C028-15AI CY7C028-15AXI 20 CY7C028-20AC CY7C028-20AI 32K x18 Asynchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 12 CY7C037-12AC 15 CY7C037-15AC 20 CY7C037-20AC 64K x18 Asynchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 12 CY7C038-12AC ...
Page 19
Package Diagram 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100 100-Pin Pb-Free Thin Plastic Quad Flat Pack (TQFP) A100 All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-06042 Rev. ...
Page 20
... PCX Document #: 38-06042 Rev. *C Description of Change Change from Spec number: 38-00666 to 38-06042 Power up requirements added to Maximum Ratings Information Removed cross information from features section Added Pb-Free Logo Added Pb-Free parts to ordering information: CY7C027-20AXC, CY7C028-12AXC, CY7C028-15AXC, CY7C028-15AI, CY7C028-15AXI CY7C027/028 CY7C037/038 Page [+] Feedback ...