CY7C028V-20AI Cypress Semiconductor Corporation., CY7C028V-20AI Datasheet
CY7C028V-20AI
Specifications of CY7C028V-20AI
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CY7C028V-20AI Summary of contents
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... Features • True Dual-Ported memory cells which allow simultaneous access of the same memory location • 32K x 16 organization (CY7C027V) • 64K x 16 organization (CY7C028V) • 32K x 18 organization (CY7C037V) • 64K x 18 organization (CY7C038V) • 0.35-micron CMOS for optimum speed/power • High-speed access: 15/20/25 ns • ...
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... VCC 15 R/WL 16 OEL 17 GND 18 GND 19 I/O15L 20 I/O14L 21 I/O13L 22 I/O12L 23 I/O11L 24 I/O10L Note: 5. This pin is NC for CY7C027V. Document #: 38-06078 Rev. *A 100-Pin TQFP (Top View CY7C028V (64K x 16) CY7C027V (32K x 16 CY7C027V/028V CY7C037V/038V A9R 74 A10R 73 A11R 72 A12R 71 A13R 70 A14R 69 A15R LBR 65 UBR ...
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Pin Configurations (continued) 100 99 98 A9L 1 A10L 2 A11L 3 A12L 4 A13L 5 A14L 6 [6] A15L 7 LBL 8 UBL 9 CE0L 10 CE1L 11 SEML 12 R/WL 13 OEL 14 VCC 15 GND 16 I/O17L ...
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... CY7C027V/37V, FFFF for the CY7C028V/38V) is the mailbox for the right port and the second-highest memory location (7FFE for the CY7C027V/37V, FFFE for the CY7C028V/38V) is the mailbox for the left port. When one port writes to the other port’s mailbox, an interrupt is generated to the owner. ...
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Also, an active busy to a port prevents that port from reading its own mailbox and, thus, resetting the interrupt to it application does not require message passing, do not connect the interrupt pin to the processor’s interrupt ...
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... Input Capacitance IN C Output Capacitance OUT Notes: 7. Pulse width < 20 ns. 8. Industrial parts are available in CY7C028V and CY7C038V only 1/t = All inputs cycling 1/t (except output enable means no address or control lines change. This applies only to inputs at CMOS level standby I MAX ...
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AC Test Loads and Waveforms 3. 590Ω OUTPUT 435Ω (a) Normal Load (Load 1) Switching Characteristics Over the Operating Range Parameter Description Read Cycle t Read Cycle Time RC t Address to ...
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Switching Characteristics Over the Operating Range Parameter Description t Data Hold From Write End HD [14, 15] t R/W LOW to High Z HZWE [14 ,15] t R/W HIGH to Low Z LZWE [41] t Write Pulse to Data Delay ...
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Switching Waveforms Read Cycle No. 1 (Either Port Address Access) ADDRESS t OHA DATA OUT PREVIOUS DATA VALID Read Cycle No. 2 (Either Port CE/OE Access) CE and DATA OUT I CC CURRENT I SB [20, ...
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Switching Waveforms (continued) Write Cycle No. 1: R/W Controlled Timing ADDRESS OE [29,30 R/W NOTE 32 DATA OUT DATA IN Write Cycle No Controlled Timing ADDRESS [29,30 R/W DATA IN Notes: 25. ...
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Switching Waveforms (continued) Semaphore Read After Write Timing, Either Side A –A VALID ADRESS 0 2 SEM I R/W OE Timing Diagram of Semaphore Contention A – R/W L SEM L A – ...
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Switching Waveforms (continued) Timing Diagram of Read with BUSY (M/S=HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Write Timing with Busy Input (M/S=LOW) R/W BUSY Note: 38 LOW. ...
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Switching Waveforms (continued) Busy Timing Diagram No. 1 (CE Arbitration) CE Valid First: L ADDRESS L BUSY R CE Valid First: R ADDRESS L BUSY L Busy Timing Diagram No. 2 (Address ...
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... Switching Waveforms (continued) Interrupt Timing Diagrams Left Side Sets INT : R ADDRESS WRITE 7FFF (FFFF for CY7C028V/38V R/W L INT R t INS Right Side Clears INT : R ADDRESS R INT R Right Side Sets INT : L ADDRESS WRITE 7FFE (FFFE for CY7C028V/38V R/W R INT L t INS Left Side Clears INT ...
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... Left port writes 1 to semaphore Right port writes 0 to semaphore Right port writes 1 to semaphore Left port writes 0 to semaphore Left port writes 1 to semaphore Notes: 42. A and A ,FFFF/FFFE for the CY7C028V/038V. 0L–15L 0R–15R 43. If BUSY =L, then no change. R 44. If BUSY =L, then no change. ...
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... CY7C027V-15AC CY7C027V-15AXC 20 CY7C027V-20AC CY7C027V-20AXC 25 CY7C027V-25AC CY7C027V-25AXC 64K x16 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code 15 CY7C028V-15AC CY7C028V-15AXC 20 CY7C028V-20AC CY7C028V-20AXC CY7C028V-20AI CY7C028V-20AXI 25 CY7C028V-25AC CY7C028V-25AXC 32K x18 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code 15 CY7C037V-15AC CY7C037V-15AXC 20 CY7C037V-20AC CY7C037V-20AXC 25 CY7C037V-25AC CY7C037V-25AXC 64K x18 3.3V Asynchronous Dual-Port SRAM ...
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Package Diagram 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100 100-Pin Lead(Pb)-Free Thin Plastic Quad Flat Pack (TQFP) A100 All product and company information mentioned in this document are trademarks of their respective holders. Document #: 38-06078 Rev. *A © ...
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... Document History Page Document Title: CY7C027V/CY7C028V/CY7C037V/CY7C038V 3.3V 32K/64K x 16/18 Dual Port Static RAM Document Number: 38-06078 REV. ECN NO. Issue Date ** 237626 6/30/04 *A 259110 See ECN Document #: 38-06078 Rev. *A Orig. of Change YDT Converted data sheet from old spec 38-00670 to conform with new data sheet ...