CY7C0430BV-100BGI Cypress Semiconductor Corporation., CY7C0430BV-100BGI Datasheet
CY7C0430BV-100BGI
Specifications of CY7C0430BV-100BGI
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CY7C0430BV-100BGI Summary of contents
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... Commercial and industrial temperature ranges • 3.3V low operating power — Active = 750 mA (maximum) — Standby = 15 mA (maximum PORT 4 BUFFERED SWITCH PORT 2 PORT 3 PORT 4 REDUNDANT DATA MIRROR • 198 Champion Court • San Jose CY7C0430BV CY7C0430CV PORT 95134-1709 • 408-943-2600 Revised May 23, 2006 [+] Feedback ...
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... One cycle is required with chip enables asserted to reactivate the outputs. The CY7C0430BV and CY7C0430CV (64K × 18 device) supports burst contains for simple array partitioning. Counter enable inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast interleaved memory applications. A port’ ...
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... Master Reset. [2] MRST TMS TCK TDI CLKBIST Port 1 I/O Port 1 64K × 18 QuadPort DSE Array Port 2 [3] Port 2 Logic Blocks CY7C0430BV CY7C0430CV Reset Logic JTAG Controller TDO BIST [3] Port 4 Logic Blocks Port 4 Port 3 [3] Port 3 Logic Blocks Page [+] Feedback ...
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... CNTINT P1 Document #: 38-06027 Rev Port-1 I/O Control 9 Addr. Read Port 1 Readback Register Port 1 Mask Register Port 1 Address Port 1 Decode Counter/ Address Register Port 1 R/W P1 Interrupt CE 0P1 CE Logic 1P1 OE P1 CLK P1 MRST CY7C0430BV CY7C0430CV 64K × 18 QuadPort DSE Array INT P1 Page [+] Feedback ...
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... VSS VSS VDD VDD2 VSS2 VSS2 I/ I/O0 VSS2 P2 P3 I/O8 I/O4 I/O2 MRST CLKBIST I/O2 I/ 1/O7 I/O5 I/O3 I/O1 I/O1 I/O3 I/ CY7C0430BV CY7C0430CV I/O16 I/O9 I/O11 I/O13 I/O15 I/O17 I/O17 I/O10 I/O12 I/O14 I/O16 UB VDD1 VSS2 I/O15 R/W CE0 CE1 A15 ...
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... P3 P4 burst counter with the external address present on the address pins. CNTINC Counter Increment Input. Asserting this signal LOW P3 P4 increments the burst address counter of its respective port on each rising edge of CLK. CY7C0430BV CY7C0430CV CY7C0430CV –133 –100 Unit [1] 133 100 MHz 4 ...
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... BIST Clock Input. Thermal Ground for Heat Dissipation. Ground Input. Power Input. Address Lines Ground Input. Address Lines Power Input. Data Lines Ground Input. Data Lines Power Input. CY7C0430BV CY7C0430CV Description = LOW HIGH), the data lines 0 1 from the rising CD2 ...
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... Over the Operating Range Test Conditions = −4 4 GND ≤ V ≤ Test Conditions ° MHz 3.3V CC CY7C0430BV CY7C0430CV Ambient Temperature V DD ° ° 3.3V ± 150 +70 C ° ° 3.3V ± 150 mV – +85 C –100 Max. Min. Typ. Max. Unit 2 ...
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... R = 50Ω 0 OUTPUT C [ 1.5V TH (a) Normal Load 1.5V 50Ω TDO Z =50Ω GND (c) TAP Load Note: 5. Test conditions pF. Document #: 38-06027 Rev 50Ω 50Ω 0 OUTPUT 50Ω 50Ω 0 OUTPUT (b) Three-State Delay 3.0V 90% 90% 10% 10% GND t R All Input Pulses CY7C0430BV CY7C0430CV = 1. Page [+] Feedback ...
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... MHz. t Min. for commercial is 7.4 ns. MAX2 CYC2 8. This parameter is guaranteed by design, but it is not production tested. 9. Valid for both address and data outputs. Document #: 38-06027 Rev. *B [6] CY7C0430BV and CY7C0430CV –133 –100 Min. Max. Min. 133 7.5 10 ...
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... TDI Hold after TCK Clock Rise TDIH t TCK Clock Low to TDO Valid TDOV t TCK Clock Low to TDO Invalid TDOX f Maximum CLKBIST Frequency BIST t CLKBIST High Time BH t CLKBIST Low Time BL Document #: 38-06027 Rev. *B CY7C0430BV CY7C0430CV [6] CY7C0430BV and CY7C0430CV –133 –100 Min. Max. Min. Max ...
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... S 11. To Reset the test port without resetting the device, TMS must be held low for five clock cycles. Document #: 38-06027 Rev TMSH t TMSS t t TDIS TDIH t TDOX t TDOV t CYC2 t CL2 RSR ACTIVE CY7C0430BV CY7C0430CV t TCYC Page [+] Feedback ...
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... Addresses do not have to be accessed sequentially. Note 13 indicates that address is constantly loaded on the rising edge of the CLK. Numbers are for reference only. 16 internal signal VIL and Document #: 38-06027 Rev CL2 A A n+1 n+2 t CD2 CKLZ . IH following the next rising edge of the clock CY7C0430BV CY7C0430CV n n+1 n+2 t OHZ t OLZ t OE Page [+] Feedback ...
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... CKLZ n+1 n CD2 CKHZ Q n Read No Operation . constantly loads the address on the rising edge of the CLK; numbers are for reference only. IL CY7C0430BV CY7C0430CV CD2 CKHZ CKHZ CKLZ CD2 CKHZ CD2 CKLZ A A n+3 n+4 t CD2 t CKLZ Write Read Page ...
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... The “Internal Address” is equal to the “External Address” when CNTLD = V Document #: 38-06027 Rev. *B [19, 20, 21, 22 n+1 n+2 n n+2 n+3 t CD2 OHZ Read Write [23, 24 SCINC HCINC t CD2 n+1 DC Counter Hold Read with Counter . CY7C0430BV CY7C0430CV A A n+4 n+5 t CD2 Q n+4 t CKLZ Read Q Q n+2 n+3 Read with Counter Page [+] Feedback ...
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... CNTINC t t SCINC HCINC D D DATA Write External Address Note CNTRST = MRST = MKLD = MKRD = CNTRD = Document #: 38-06027 Rev. *B [24, 25 n+1 n+1 n+2 Write with Write Counter Counter Hold IH. CY7C0430BV CY7C0430CV n+2 n+3 n n+3 n+4 Write with Counter Page [+] Feedback ...
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... DATA OUT Counter Reset Notes: 26 MRST = MKLD = MKRD = CNTRD = 27. No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset. Document #: 38-06027 Rev Write Read Address 0 Address 0 Address CY7C0430BV CY7C0430CV n n HCLD SCLD A n Read Read ...
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... This is the value of the address counter being read out on the address lines. Document #: 38-06027 Rev HCINC t SCRD A A n+1 n CD2 n+1 Read Data with Counter . IH in next clock cycle. CKLZ . CKHZ CY7C0430BV CY7C0430CV Note 29 Note 30 t CA2 t t CKHZ CKLZ [31] A n+2 t HCRD A A n+2 n CKLZ CKHZ Q Q n+2 ...
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... Mask Register Value Notes: 32 R/W = CNTRST = MRST = CNTLD = CNTRD = CNTINC = 33. This is the value of the Mask Register read out on the address lines. Document #: 38-06027 Rev. *B Note 29 t CKLZ t t SMRD HMRD Read Mask Register Value . IH CY7C0430BV CY7C0430CV Note 30 t CA2 t CKHZ [33 Page [+] Feedback ...
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... Port 2 will read the most recent data (written by Port 1) (t CCS Document #: 38-06027 Rev CKLZ t CCS CD2 CYC2 CY7C0430BV CY7C0430CV violated, indeterminate CCS + t ) after the rising edge of Port 2’s clock. If CYC2 CD2 ) after the rising edge of Port 2’s clock. CD2 Page [+] Feedback ...
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... Interrupt flag is set with respect to the rising edge of the write clock, and is reset with respect to the rising edge of the read clock. Document #: 38-06027 Rev HCLD t t HCINC SCINC xx7Dh xx7Eh SINT t RINT t HA FFFE A m CY7C0430BV CY7C0430CV xx7Fh xx00h xx00h t t SCINT RCINT A A n+2 n m+3 m Page [+] Feedback ...
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... Load of Address Lines into Mask Register Load Load of Address Lines into Counter/Address Register Increment Counter Increment Readback Readback Counter on Address Lines Readback Readback Mask Register on Address Lines Hold Counter Hold CY7C0430BV CY7C0430CV Operation Deselected Deselected Write Read Outputs Disabled [45, 48, 49] Operation Page [+] Feedback ...
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... P2 0P3–15P3 L FFFF X FFFF FFFE X FFFE H X FFFD FFFD X FFFC X FFFC LBI = UBI = R/WI = MKLDI = MKRDI = CNTRDI = CNTRSTI = CNTLDI = 0I CY7C0430BV CY7C0430CV flag, a write by P1 LOW. A read P1 HIGH. When one P1 Port 3 Port 4 INT A INT P3 0P4–15P4 P4 X FFFF FFFE FFFD ...
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... Mask Register Read signal (MKRD). Both signals are synchronized to the port's clock as shown in Table 2. Counter read has a higher priority than mask read. Readback Register Addr. Readback Mask Register Counter/ Address Register CY7C0430BV CY7C0430CV ). When the address readback from the CA2 Memory Array Page [+] Feedback ...
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... FFFF (64K). The mask register load operation has a higher priority over the address counter load opera- tion. 2. Increment: Once the address counter is loaded with an external address, the counter can internally increment the address value by asserting CNTINC LOW. The counter can CY7C0430BV CY7C0430CV ...
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... IEEE 1149.1 Serial Boundary Scan (JTAG) and Memory Built-In-Self-Test (MBIST) The CY7C0430BV and CY7C0430CV incorporate a serial boundary scan test access port (TAP). This port is fully compatible with IEEE Standard 1149.1-2001 operates using JEDEC standard 3.3V I/O logic levels composed of three input connections and one output connection required by the test logic defined by the standard ...
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... Control Register (MCR) is loaded with the default value “00”, loaded into the and the TAP controller’s finite state machine (FSM), which is synchronous to TCK, transitions to Run Test/Idle state. The entire MBIST test will be performed with a deterministic CY7C0430BV CY7C0430CV Page [+] Feedback ...
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... Input only and output only signals have an extra dummy cell (odd cells) that are used to ease device layout. P3_IO(17-9) P2_IO(17-9) P3_IO(8-0) P2_IO(8- Figure 3. MBIST Debug Register Packet CY7C0430BV CY7C0430CV 62 P1_IO(17-9) 26 P1_IO(8-0) Page [+] Feedback ...
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... The “0”/”1” next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-06027 Rev. *B [53] 1 SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT- EXIT1- PAUSE- EXIT2-DR 1 UPDATE- CY7C0430BV CY7C0430CV 1 SELECT IR-SCAN 0 1 CAPTURE-IR 0 SHIFT- EXIT1- PAUSE- EXIT2-IR 1 UPDATE- Page ...
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... MBIST Debug Register (MDR) 391 0 Boundary Scan Register (BSR) TAP CONTROLLER Value Reserved for version number Defines Cypress part number Allows unique identification of QuadPort DSE device vendor Indicate the presence register CY7C0430BV CY7C0430CV Selection TDO Circuitry (MUX) TCK TMS MRST Description Page ...
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... Down count from 64K to 0. MIA_r0w1r1. Down count MIA_r1w0r0. Read all 0s. Port 1 write all zeros to memory using March2 Algorithm (M2A). Up count M2A_r0w1r1. Up count M2A_r1w0r0. Down count M2A_r0w1r1. Down count M2A_r1w0r0. Read all 0s. Port 1 writes topological checkerboard data to memory. CY7C0430BV CY7C0430CV Bit Size Page [+] Feedback ...
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... Port 4 writes every address value into its memory location (UAA). All ports read UAA data. Port 4 writes all ones to memory. Port 4 writes inverse address value into memory. All ports read inverse UAA data. Test complete. Mode Debug Reserved Reserved CY7C0430BV CY7C0430CV Description Page [+] Feedback ...
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... IO1_P3 148 IO2_P3 150 IO3_P3 152 IO4_P3 154 IO5_P3 156 IO6_P3 158 IO7_P3 160 IO8_P3 162 IO0_P1 164 IO1_P1 CY7C0430BV CY7C0430CV Signal Name Bump (Ball) ID T20 T19 U19 U18 V20 V19 R17 L18 N18 N17 P17 T17 T18 Y20 W19 U17 ...
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... CNTRST_P1 296 MKLD_P1 298 CNTLD_P1 300 CNTINC_P1 302 CNTRD_P1 304 MKRD_P1 306 LB_P1 308 UB_P1 310 OE_P1 312 R/W_P1 314 CE1_P1 316 CE0_P1 318 INT_P1 320 CLK_P1 322 IO9_P2 324 IO10_P2 326 IO11_P2 328 IO12_P2 CY7C0430BV CY7C0430CV Signal Name Bump (Ball ...
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... B14 Ordering Information 10 Gb/s 3.3V QuadPort DSE Family 1 Mb (64K × 18) Speed (MHz) Ordering Code 133 CY7C0430BV-133BGI CY7C0430CV-133BGI 100 CY7C0430BV-100BGC CY7C0430BV-100BGI Document #: 38-06027 Rev. *B Bump (Ball) ID Package Name Package Type BG272 272-ball Grid Array (BGA) BG272 272-ball Grid Array (BGA) BG272 ...
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... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C0430BV CY7C0430CV ...
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... Document History Page Document Title: CY7C0430BV, CY7C0430CV 10 Gb/s 3.3V QuadPort DSE Family Document Number: 38-06027 Issue Orig. of REV. ECN NO. Date Change ** 109906 09/10/01 *A 115042 05/23/02 *B 464083 SEE ECN Document #: 38-06027 Rev. *B Description of Change SZV Change from Spec number: 38-01052 to 38-06027 FSG ...