CY7C09079V-12AC Cypress Semiconductor Corporation., CY7C09079V-12AC Datasheet

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CY7C09079V-12AC

Manufacturer Part Number
CY7C09079V-12AC
Description
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

Specifications of CY7C09079V-12AC

Case
QFP-100L

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C09079V-12AC
Manufacturer:
CY
Quantity:
546
Cypress Semiconductor Corporation
Document #: 38-06043 Rev. *B
Features
Notes:
CY7C09079V/89V/99V
CY7C09179V/89V/99V
1. See page 6 for Load Conditions.
2. I/O
3. A
• True Dual-Ported memory cells which allow simulta-
• 6 Flow-Through/Pipelined devices
• 3 Modes
• Pipelined output mode on both ports allows fast
• 0.35-micron CMOS for optimum speed/power
Logic Block Diagram
R/W
OE
CE
CE
FT/Pipe
I/O
A
CLK
ADS
CNTEN
CNTRST
neous access of the same memory location
— 32K x 8/9 organizations (CY7C09079V/179V)
— 64K x 8/9 organizations (CY7C09089V/189V)
— 128K x 8/9 organizations (CY7C09099V/199V)
— Flow-Through
— Pipelined
— Burst
100-MHz operation
0
0
–A
–A
0
0L
L
0L
1L
–I/O
L
L
L
14
–I/O
[3]
14/15/16L
for 32K, A
7
L
L
for x8 devices, I/O
[2]
L
7/8L
0
–A
15/16/17
15
for 64K, and A
0
–I/O
8/9
0/1
8
0/1
1
0
1
Counter/
Register
Address
for x9 devices.
Decode
0
–A
16
0
for 128K devices.
3901 North First Street
Control
I/O
True Dual-Ported
RAM Array
Synchronous Dual-Port Static RAM
• High-speed clock to data access 6.5
• 3.3V low operating power
• Fully synchronous interface for easier operation
• Burst counters increment addresses internally
• Dual Chip Enables for easy depth expansion
• Automatic power-down
• Commercial and Industrial temperature ranges
• Available in 100-pin TQFP
• Pb-Free packages available
(max.)
— Active= 115 mA (typical)
— Standby= 10 µA (typical)
— Shorten cycle times
— Minimize bus noise
— Supported in Flow-Through and Pipelined modes
Control
I/O
3.3V 32K/64K/128K x 8/9
San Jose
0
Counter/
Address
Register
Decode
,
CY7C09079V/89V/99V
CY7C09179V/89V/99V
CA 95134
0/1
1
1
0
0/1
8/9
Revised May 18, 2005
15/16/17
[1]
/7.5
408-943-2600
A
I/O
[1]
0
–A
/9/12 ns
CNTRST
0R
FT/Pipe
CNTEN
14/15/16R
–I/O
[3]
ADS
R/W
CLK
CE
CE
OE
[2]
7/8R
0R
1R
R
R
R
R
R
R
R
[+] Feedback

Related parts for CY7C09079V-12AC

CY7C09079V-12AC Summary of contents

Page 1

... CY7C09079V/89V/99V CY7C09179V/89V/99V Features • True Dual-Ported memory cells which allow simulta- neous access of the same memory location • 6 Flow-Through/Pipelined devices — 32K x 8/9 organizations (CY7C09079V/179V) — 64K x 8/9 organizations (CY7C09089V/189V) — 128K x 8/9 organizations (CY7C09099V/199V) • 3 Modes — Flow-Through — Pipelined — ...

Page 2

... When writing simultaneously to the same location, the final value cannot be guaranteed. 5. This pin is NC for CY7C09079V. 6. This pin is NC for CY7C09079V and CY7C09089V. 7. For CY7C09079V and CY7C09089V, pin #23 connected to V compatible with an IDT 5V x16 flow-through device. Document #: 38-06043 Rev HIGH on CE ...

Page 3

... CY7C09189V (64K x 9) CY7C09179V (32K CY7C09079V/89V/99V CY7C09079V/89V/99V CY7C09179V/89V/99V CY7C09179V/89V/99V [ 7.5 155 25 10 µA CY7C09079V/89V/99V CY7C09179V/89V/99V A7R 72 A8R 71 A9R 70 A10R 69 A11R 68 A12R 67 A13R 66 A14R [8] 65 A15R [9] 64 A16R 63 GND CE0R 57 CE1R 56 CNTRSTR 55 R/WR 54 OER 53 FT/PIPER 52 GND CY7C09079V/89V/99V CY7C09179V/89V/99V -9 - 135 115 µA 10 µA Page [+] Feedback ...

Page 4

... Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage............................................ >2001V Latch-Up Current ..................................................... >200 mA ° ° +150 C Operating Range ° ° +125 C Range Commercial +0.5V CC [11] Industrial +0.5V CC CY7C09079V/89V/99V CY7C09179V/89V/99V for 128K devices). 16 AND CE must be asserted MAX for x9 devices). 8 Ambient Temperature V CC ° ° 3.3V ± 300 mV 0 ...

Page 5

... Ind. 10 250 Com’l. 105 135 95 125 [11] Ind. 125 170 Test Conditions ° MHz 3.3V CC AND CE must be asserted to their active states ( CY7C09079V/89V/99V CY7C09179V/89V/99V -9 -12 2.4 2.4 V 0.4 0.4 V 2.0 2.0 V 0.8 0.8 V µA –10 10 –10 10 135 225 115 205 mA 185 ...

Page 6

... TH OUTPUT 1.4V TH (b) Thévenin Equivalent (Load 1) [13] 3.0V 10% GND ≤ Capacitance (pF) (b) Load Derating Curve CY7C09079V/89V/99V CY7C09179V/89V/99V 3. 590Ω OUTPUT 435Ω (c) Three-State Delay (Load 2) (Used for & t CKLZ OLZ OHZ including scope and jig) ALL INPUT PULSES 90% 90% 10% ≤ ...

Page 7

... Write Port Clock HIGH to Read Data Delay CWDD t Clock to Clock Set-Up Time CCS Notes: 14. Test conditions used are Load 2. 15. This parameter is guaranteed by design, but it is not production tested. Document #: 38-06043 Rev. *B CY7C09079V/89V/99V CY7C09179V/89V/99V CY7C09079V/89V/99V CY7C09179V/89V/99V [1] [ Min. Max. Min. Max. Min. ...

Page 8

... A A n+1 n [16, 17, 18, 19 CL2 A A n+1 n+2 t CD2 CKLZ = following the next rising edge of the clock constantly loads the address on the rising edge of the CLK. Numbers are for reference only. IL CY7C09079V/89V/99V CY7C09179V/89V/99V n+3 t CKHZ Q n+1 n OHZ OLZ n n+1 n+2 t OHZ ...

Page 9

... CD2 HC CD2 CKHZ CKLZ [22, 23, 24, 25] NO MATCH t CD1 NO MATCH t CWDD VALID . for the left port, which is being written to. IH CY7C09079V/89V/99V CY7C09179V/89V/99V CD2 CKHZ CKLZ CD2 CKHZ CD2 CKLZ t CD1 VALID >maximum specified, then data is not valid CWDD CCS Page (B1) [+] Feedback ...

Page 10

... During “No Operation”, data in memory at the selected address may be corrupted and should be re-written to ensure data integrity. Document #: 38-06043 Rev. *B [19, 26, 27, 28 n+1 n CD2 CKHZ Q n READ NO OPERATION [19, 26, 27, 28 n+1 n+2 n n+2 n+3 t CD2 OHZ READ WRITE . IH CY7C09079V/89V/99V CY7C09179V/89V/99V A A n+3 n CD2 CKLZ Q WRITE READ A A n+4 n CKLZ CD2 Q n+4 READ Page n+3 [+] Feedback ...

Page 11

... OUT OE Document #: 38-06043 Rev. *B [17, 19, 26, 27, 28 n+1 n+2 n n+2 t CD1 Q n+1 t CKHZ NO READ OPERATION [17, 20, 26, 27, 28 n+1 n+2 n n+2 n OHZ READ WRITE CY7C09079V/89V/99V CY7C09179V/89V/99V n+3 n CD1 CD1 Q n CKLZ DC WRITE READ A A n+4 n CD1 t CD1 Q n CKLZ READ Page [+] Feedback ...

Page 12

... Document #: 38-06043 Rev. *B [29] t SAD t SCN t CD2 n+1 DC COUNTER HOLD READ WITH COUNTER [29 n+1 COUNTER HOLD READ WITH COUNTER . IH CY7C09079V/89V/99V CY7C09179V/89V/99V t HAD t HCN Q Q n+2 n+3 READ WITH COUNTER t t SAD HAD t t SCN HCN Q Q n+3 n+2 READ WITH COUNTER ...

Page 13

... The “Internal Address” is equal to the “External Address” when ADS = V Document #: 38-06043 Rev. *B [30, 31 n+1 n+1 n+2 WRITE WITH WRITE COUNTER COUNTER HOLD and equals the counter output when ADS = V IL CY7C09079V/89V/99V CY7C09179V/89V/99V n+2 n+3 n n+3 n+4 WRITE WITH COUNTER . IH Page ...

Page 14

... HRST CNTRST t SD DATA DATA OUT COUNTER RESET Notes: 32 33. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset. Document #: 38-06043 Rev WRITE READ ADDRESS 0 ADDRESS 0 ADDRESS 1 CY7C09079V/89V/99V CY7C09179V/89V/99V n n READ READ ADDRESS n Page [+] Feedback ...

Page 15

... CNTRST I/O Mode Reset out( Load out( Hold out( Increment out(n+ CY7C09079V/89V/99V CY7C09179V/89V/99V Operation 9 [37] Deselected [37] Deselected Write [37] Read Outputs Disabled Operation Counter Reset to Address 0 Address Load into Counter External Address Blocked—Counter Disabled Counter Enabled—Internal Address Generation Page [+] Feedback ...

Page 16

... Ordering Information 32K x8 3.3V Synchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 6.5 CY7C09079V-6AC [1] 7.5 CY7C09079V-7AC CY7C09079V-7AI 9 CY7C09079V-9AC 12 CY7C09079V-12AC 64K x8 3.3V Synchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 6.5 CY7C09089V-6AC CY7C09089V-6AXC [1] 7.5 CY7C09089V-7AC 9 CY7C09089V-9AC 12 CY7C09089V-12AC CY7C09089V-12AXC 128K x8 3.3V Synchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 6 ...

Page 17

... Pb-Free Thin Quad Flat Pack A100 100-Pin Thin Quad Flat Pack A100 100-Pin Pb-Free Thin Quad Flat Pack A100 100-Pin Thin Quad Flat Pack A100 100-Pin Pb-Free Thin Quad Flat Pack CY7C09079V/89V/99V CY7C09179V/89V/99V Operating Range Commercial Commercial Commercial Commercial Commercial Commercial ...

Page 18

... Document History Page Document Title: CY7C09079V/89V/99V, CY7C09179V/89V/99V 3.3V 32K/64K/128K x 8/9Synchronous Dual Port Static RAM Document Number: 38-06043 Issue Orig. of REV. ECN NO. Date Change ** 110191 09/29/01 SZV *A 122293 12/27/02 RBI *B 365034 See ECN PCX Document #: 38-06043 Rev. *B CY7C09079V/89V/99V CY7C09179V/89V/99V Description of Change Change from Spec number: 38-00667 to 38-06043 ...

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