CY7C09159-12AC Cypress Semiconductor Corporation., CY7C09159-12AC Datasheet
CY7C09159-12AC
Specifications of CY7C09159-12AC
Related parts for CY7C09159-12AC
CY7C09159-12AC Summary of contents
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... Features • True Dual-Ported memory cells which allow simulta- neous access of the same memory location • 2 Flow-Through/Pipelined devices — organization (CY7C09159) — 16K x 9 organization (CY7C09169) • 3 Modes — Flow-Through — Pipelined — Burst • Pipelined output mode on both ports allows fast 100-MHz cycle time • ...
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... Functional Description The CY7C09159 and CY7C09169 are high speed synchro- nous CMOS 8K and 16K x 9 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory. control, address, and data lines allow for minimal set-up and hold times ...
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... A7L 3 A8L 4 A9L 5 A10L 6 A11L 7 A12L 8 [Note 3] A13L VCC CE0L 18 CE1L 19 CNTRSTL 20 R/WL 21 OEL 22 FT/PIPEL Note: 3. This pin is NC for CY7C09159. PRELIMINARY 100-Pin TQFP (Top View CY7C09169 (16K x 9) CY7C09159 ( CY7C09159 CY7C09169 A7R 72 A8R 71 A9R 70 A10R 69 A11R 68 A12R 67 A13R [Note 3] 66 ...
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... –I/O for x8 devices; I Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage ........................................... >2001V Latch-Up Current..................................................... >200 mA Operating Range Range Commercial Industrial 4 CY7C09159 CY7C09169 CY7C09159 CY7C09159 CY7C09169 CY7C09169 -7 - 7.5 12 235 195 40 30 0.05 0.05 AND CE must be asserted MAX –I/O for x9 devices). ...
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... 250 TH OUTPUT (b) Thévenin Equivalent (Load 1) ALL INPUT PULSES 3.0V 90% 90% 10% 10% GND 3 ns AND CE must be asserted to their active states ( CY7C09159 CY7C09169 -7 -12 Typ Max Min Typ Max 2.4 0.4 0.4 2.2 0.8 0 235 420 195 300 260 445 225 ...
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... Port to Port Delays t Write Port Clock HIGH to Read Data Delay CWDD t Clock to Clock Set-up Time CCS PRELIMINARY -6 Min Max 53 100 19 10 6.5 6 3.5 0 3.5 0 3.5 0 3.5 0 3.5 0 3 CY7C09159 CY7C09169 CY7C09159 CY7C09169 -7 -12 Min Max Min Max Units 45 33 MHz 83 50 MHz 7 7 ...
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... DC CD1 Q n [5,6,7, CYC2 t CL2 A A n+1 n+2 t CD2 CKLZ = following the next rising edge of the clock constantly loads the address on the rising edge of the CLK. Numbers are for reference only CY7C09159 CY7C09169 n+3 t CKHZ Q Q n+1 n OHZ OLZ n n+1 t ...
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... CCS CD1 CWDD PRELIMINARY CD2 HC CD2 [11,12,13,14] NO MATCH t CD1 MATCH t CWDD VALID . for the Left Port, which is being written to CY7C09159 CY7C09169 CD2 CKHZ CKHZ CKLZ CD2 CKHZ CD2 CKLZ CKLZ NO t CD1 VALID >maximum specified, then data is not valid CWDD CCS D 4 ...
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... During “No operation”, data in memory at the selected address may be corrupted and should be re-written to ensure data integrity. PRELIMINARY [8,12,15,16 n+1 n CD2 CKHZ Q n READ NO OPERATION [8,12,15,16 n+1 n+2 n n+2 n+3 t CD2 OHZ READ WRITE 9 CY7C09159 CY7C09169 A A n+3 n CD2 CKLZ WRITE READ A A n+4 n CKLZ CD2 Q n+4 READ Q n+3 ...
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... CL1 CLK R ADDRESS DATA IN t CD1 Q DATA OUT OE PRELIMINARY [6,8,12,15 n+1 n+2 n n+2 t CD1 Q n+1 t CKHZ NO READ OPERATION [6,8,12,15 n+1 n+2 n n+2 n OHZ READ WRITE 10 CY7C09159 CY7C09169 n+3 n CD1 CD1 Q n CKLZ WRITE READ A A n+4 n CD1 t CD1 Q n CKLZ DC READ ...
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... CE , R/W and CNTRST = PRELIMINARY [17] t SAD t SCN t CD2 n COUNTER HOLD READ WITH COUNTER [17 n+1 READ WITH COUNTER . IH 11 CY7C09159 CY7C09169 t HAD t HCN Q n+2 READ WITH COUNTER t t SAD HAD t t SCN HCN Q n+2 n+3 COUNTER HOLD COUNTER Q n+3 READ WITH ...
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... IH 19. The “Internal Address” is equal to the “External Address” when ADS = V PRELIMINARY A n n+1 n+1 n+2 WRITE WITH WRITE COUNTER COUNTER HOLD . and equals the counter output when ADS = CY7C09159 CY7C09169 [18,19 n+2 n n+3 n+4 WRITE WITH COUNTER . IH A n+4 ...
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... CNTEN t t SRST HRST CNTRST t SD DATA DATA OUT COUNTER RESET Notes: 20 21. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset. PRELIMINARY WRITE READ ADDRESS 0 ADDRESS 0 13 CY7C09159 CY7C09169 n n READ READ ADDRESS 1 ADDRESS ...
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... Deselected D Write IN [25] D Read OUT High-Z Outputs Disabled [22,26,27,28] CNTEN CNTRST I/O Mode Reset out( Load out( Hold out( Increment out(n+ CY7C09159 CY7C09169 Operation Counter Reset to Address 0 Address Load into Counter External Address Blocked—Counter Disabled Counter Enabled—Internal Address Generation ...
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... Ordering Information 8K x9 Synchronous Dual-Port SRAM Speed (ns) Ordering Code 6.5 CY7C09159-6AC 7.5 CY7C09159-7AC CY7C09159-7AI 12 CY7C09159-12AC CY7C09159-12AI 16K x9 Synchronous Dual-Port SRAM Speed (ns) Ordering Code 6.5 CY7C09169-6AC 7.5 CY7C09169-7AC CY7C09169-7AI 12 CY7C09169-12AC CY7C09169-12AI Document #: 38–00671–B Package Diagram © Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product ...