CY7C09289V-7AC Cypress Semiconductor Corporation., CY7C09289V-7AC Datasheet

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CY7C09289V-7AC

Manufacturer Part Number
CY7C09289V-7AC
Description
3.3V 16K/32K/64K x 16/18 Synchronous Dual-Port Static RAM
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

Specifications of CY7C09289V-7AC

Case
QFP-100L

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C09289V-7AC
Manufacturer:
CYPRESS
Quantity:
319
1CY7C025/0251
Cypress Semiconductor Corporation
Document #: 38-06056 Rev. *B
CY7C09269V CY7C09279V CY7C09289V CY7C09369V CY7C09379V CY7C09389V3.3V 16K/32K/64K x 16/18
Synchronous Dual-Port Static RAM
Features
Notes:
Logic Block Diagram
1. Call for availability.
2. See page 6 for Load Conditions.
3. I/O
4. I/O
5. A
• True Dual-Ported memory cells which allow simulta-
• 6 Flow-Through/Pipelined devices
• 3 Modes
• Pipelined output mode on both ports allows fast
• 0.35-micron CMOS for optimum speed/power
R/W
UB
CE
CE
LB
OE
FT/Pipe
I/O
I/O
A
CLK
ADS
CNTEN
CNTRST
neous access of the same memory location
— 16K x 16/18 organization (CY7C09269V/369V)
— 32K x 16/18 organization (CY7C09279V/379V)
— 64K x 16/18 organization (CY7C09289V/389V)
— Flow-Through
— Pipelined
— Burst
100-MHz operation
0L
0
–A
L
8/9L
0L
8
0
L
0L
1L
L
–A
–I/O
–I/O
L
L
L
13
–I/O
13/14/15L
–I/O
[5]
for 16K; A
15
7
L
L
for x16 devices. I/O
L
for x16 devices; I/O
7/8L
[3]
[4]
15/17L
0
–A
14/15/16
14
for 32K; A
8/9
8/9
0
9
–I/O
–I/O
0/1
0/1
0
1
0
8
1b
Counter/
Address
Register
–A
17
Decode
for x18 devices.
b
15
for x18 devices.
0b 1a 0a
for 64K devices.
a
3901 North First Street
Control
I/O
True Dual-Ported
Synchronous Dual-Port Static RAM
RAM Array
• High-speed clock to data access 6.5
• 3.3V low operating power
• Fully synchronous interface for easier operation
• Burst counters increment addresses internally
• Dual Chip Enables for easy depth expansion
• Upper and Lower Byte Controls for Bus Matching
• Automatic power-down
• Commercial and Industrial temperature ranges
• Pb-Free 100-pin TQFP Package Available
(max.)
— Active = 115 mA (typical)
— Standby = 10 µA (typical)
— Shorten cycle times
— Minimize bus noise
— Supported in Flow-Through and Pipelined modes
Control
I/O
3.3V 16K/32K/64K x 16/18
San Jose
0a
a
1a
Counter/
Register
Address
Decode
CY7C09269V/79V/89V
CY7C09369V/79V/89V
0b
b
CA 95134
1b
0/1
1
0
0/1
8/9
8/9
14/15/16
Revised April 6, 2005
[1, 2]
I/O
A
/7.5
8/9R
408-943-2600
I/O
0R
–A
[2]
0R
CNTRST
–I/O
FT/Pipe
CNTEN
/9/12 ns
13/14/15R
–I/O
[5]
ADS
R/W
15/17R
CLK
CE
CE
OE
UB
LB
[3]
[4]
7/8R
0R
1R
R
R
R
R
R
R
R
R
R
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Related parts for CY7C09289V-7AC

CY7C09289V-7AC Summary of contents

Page 1

... CY7C09269V CY7C09279V CY7C09289V CY7C09369V CY7C09379V CY7C09389V3.3V 16K/32K/64K x 16/18 Synchronous Dual-Port Static RAM 1CY7C025/0251 Features • True Dual-Ported memory cells which allow simulta- neous access of the same memory location • 6 Flow-Through/Pipelined devices — 16K x 16/18 organization (CY7C09269V/369V) — 32K x 16/18 organization (CY7C09279V/379V) — ...

Page 2

... All parts are available in 100-pin Thin Quad Plastic Flatpack (TQFP) packages. 100-Pin TQFP (Top View CY7C09289V (64K x 16) CY7C09279V (32K x 16) CY7C09269V (16K x 16 pin compatible to an IDT 5V x16 pipelined device; connecting pin #18 and #58 to GND is pin ...

Page 3

Pin Configurations (continued) 100 A9L 1 A10L 2 A11L 3 A12L 4 A13L 5 A14L 6 [10] A15L 7 [11] LBL 8 UBL 9 CE0L 10 CE1L 11 CNTRSTL 12 R/WL 13 OEL 14 VCC 15 ...

Page 4

Pin Definitions Left Port Right Port A –A A –A Address Inputs (A 0L 15L 0R 15R ADS ADS Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW access the part using ...

Page 5

Electrical Characteristics Over the Operating Range Parameter Description V Output HIGH Voltage ( –4.0 mA Output LOW Voltage ( +4.0 mA Input HIGH Voltage IH V Input LOW ...

Page 6

AC Test Loads 3. 590Ω OUTPUT 435Ω (a) Normal Load (Load 1) AC Test Loads (Applicable to -6 and -7 only 50Ω 50Ω 0 OUTPUT ...

Page 7

Switching Characteristics Over the Operating Range Parameter Description f f Flow-Through MAX1 Max f f Pipelined MAX2 Max t Clock Cycle Time - Flow-Through CYC1 t Clock Cycle Time - Pipelined CYC2 t Clock HIGH Time - Flow-Through CH1 t ...

Page 8

Switching Waveforms Read Cycle for Flow-Through Output (FT/PIPE = V t CYC1 t CH1 CLK R ADDRESS t CD1 DATA OUT t ...

Page 9

Switching Waveforms (continued) [21, 22] Bank Select Pipelined Read t CYC2 t t CH2 CL2 CLK ADDRESS A (B1 0(B1) DATA OUT(B1 ADDRESS A (B2) ...

Page 10

Switching Waveforms (continued) Pipelined Read-to-Write-to-Read ( CYC2 t t CH2 CL2 CLK R ADDRESS DATA IN DATA OUT ...

Page 11

Switching Waveforms (continued) Flow-Through Read-to-Write-to-Read ( CYC1 t t CH1 CL1 CLK R ADDRESS DATA IN t CD1 ...

Page 12

Switching Waveforms (continued) Pipelined Read with Address Counter Advance t CYC2 t t CH2 CL2 CLK ADDRESS SAD HAD ADS CNTEN t t SCN HCN DATA OUT ...

Page 13

Switching Waveforms (continued) Write with Address Counter Advance (Flow-Through or Pipelined Outputs) t CYC2 t t CH2 CL2 CLK ADDRESS n INTERNAL A n ADDRESS t t SAD HAD ADS CNTEN t t SCN HCN ...

Page 14

Switching Waveforms (continued) [20, 27, 33, 34] Counter Reset (Pipelined Outputs) t CYC2 t t CH2 CL2 CLK ADDRESS INTERNAL A X ADDRESS SAD HAD ADS t t SCN HCN CNTEN t t SRST HRST ...

Page 15

Read/Write and Enable Operation Inputs OE CLK Address Counter Control Operation Previous Address Address CLK ADS CNTEN ...

Page 16

... CY7C09279V-7AXC 9 CY7C09279V-9AC CY7C09279V-9AI 12 CY7C09279V-12AC CY7C09279V-12AXC 64K x16 3.3V Synchronous Dual-Port SRAM Speed (ns) Ordering Code [1, 2] 6.5 CY7C09289V-6AC CY7C09289V-6AXC [2] 7.5 CY7C09289V-7AC CY7C09289V-7AXC 9 CY7C09289V-9AC CY7C09289V-9AXC CY7C09289V-9AI CY7C09289V-9AXI 12 CY7C09289V-12AC CY7c09289V-12AXC Document #: 38-06056 Rev. *B Package Name Package Type A100 100-Pin Thin Quad Flat Pack A100 ...

Page 17

Synchronous Dual-Port SRAM Speed (ns) Ordering Code [1, 2] 6.5 CY7C09369V-6AC CY7C09369V-6AXC [2] 7.5 CY7C09369V-7AC CY7C09269V-7AXC CY7C09369V-7AI 9 CY7C09369V-9AC CY7C09369V-9AXC CY7C09369V-9AI 12 CY7C09369V-12AC CY7C09369V-12AXC 32K x18 3.3V Synchronous Dual-Port SRAM Speed (ns) Ordering Code [1, 2] 6.5 ...

Page 18

Package Diagram 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100 100-Pin Pb-Free Thin Plastic Quad Flat Pack (TQFP) A100 All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-06056 Rev. ...

Page 19

Document History Page Document Title: CY7C09269V/79V/89V CY7C09369V/79V/89V 3.3V 16K/32K/64K X 16/18 Synchronous Dual Port Static RAM Document Number: 38-06056 Issue Orig. of REV. ECN NO. Date Change ** 110215 12/18/01 *A 122306 12/27/02 *B 344354 See ECN Document #: 38-06056 ...

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