CY7C09579V-67BBC Cypress Semiconductor Corporation., CY7C09579V-67BBC Datasheet

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... CY7C09569V CY7C09579V CY7C09289V CY7C09369V CY7C09379V CY7C09389V3.3V 16K/32K x 36 FLEx36™ Synchronous Dual-Port Static RAM FLEx36™ Synchronous Dual-Port Static RAM Features • True dual-ported memory cells which allow simulta- neous access of the same memory location • Two Flow-Through/Pipelined devices — 16K x 36 organization (CY7C09569V) — ...

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... Functional Description The CY7C09569V and CY7C09579V are high-speed 3.3V synchronous CMOS 16K and 32K x 36 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory. Registers on control, address, and data lines allow for minimal set-up and hold times ...

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... A11L A12L 31 A13L I/O26L 34 I/O25L 35 I/O24L 36 Notes: 2. This pin is A14L for CY7C09579V. 3. This pin is A14R for CY7C09579V. Document #: 38-06054 Rev. *B 144-Pin Thin Quad Flatpack (TQFP) Top View CY7C09569V (16K x 36) CY7C09579V (32K x 36) CY7C09569V CY7C09579V 108 I/O33R I/O34R 107 106 I/O35R ...

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... VSS I/O16R I/O28R I/O34R I/O35R A3R VSS VSS I/O19R I/O25R I/O26R NC I/O7L I/O2L I/O2R I/O7R I/O5L I/O3L I/O0L I/O0R I/3R I/O4L VDD I/O1L I/O1R VDD CY7C09569V CY7C09579V I/O30R I/O32R A0R NC I/O27R I/O31R A1R NC A2R A5R A4R NC SIZE A7R A6R VDD CER ...

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... Big Endian Pin. See Bus Matching for details Ground Input Power Input. DD Document #: 38-06054 Rev. *B CY7C09569V CY7C09569V CY7C09579V CY7C09579V -100 -83 100 250 240 Description –A for 16K, A –A for 32K devices CY7C09569V CY7C09579V CY7C09569V CY7C09579V -67 Unit 67 MHz 8 ns 230 μ MAX Page [+] Feedback ...

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... MHz 3.3V DD CY7C09569V CY7C09579V Ambient Temperature V DD ° ° 3.3V ± 165 +70 C ° ° 3.3V ± 165 mV – +85 C CY7C09569V CY7C09579V -83 -67 Unit 2.4 2.4 V 0.4 0.4 V 2.0 2.0 V 0.8 0.8 V μA –10 10 –10 10 240 360 230 340 mA 270 ...

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... External AC Test Load Capacitance = 10 pF. 7. (Internal I/O pad Capacitance = 10 pF Test Load. Document #: 38-06054 Rev. *B OUTPUT = 1.5V TH (b) Three-State Delay (Load 2) 3.0V 90% 10 ≤ 100 200 Capacitance (pF) (b) Load Derating Curve CY7C09569V CY7C09579V 3. 590Ω 435Ω 90% 10% ≤ Page [+] Feedback ...

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... CY7C09569V CY7C09579V -67 Max. Unit 40 MHz 67 MHz Page [+] Feedback ...

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... Switching Characteristics Over the Operating Range (continued) Parameter Description Port to Port Delays t Write Port Clock HIGH to Read Data Delay CWDD t Clock to Clock Set-Up Time CCS Document #: 38-06054 Rev. *B CY7C09569V CY7C09579V -100 -83 Min. Max. Min. Max. Min CY7C09569V CY7C09579V -67 Max. Unit Page [+] Feedback ...

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... n+1 t OHZ [10, 11, 12, 13 CL2 n+1 n+2 t CD2 CKLZ following the next rising edge of the clock. IH constantly loads the address on the rising edge of the CLK. Numbers are for reference only. IL CY7C09569V CY7C09579V n+3 t CKHZ Q n OLZ n n+1 n+2 t OHZ t OLZ t ...

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... IL CL1 n 1st 2nd Cycle Cycle [10, 12, 14, 15 CD2 CD2 t CLKZ 1st Cycle only required when reading or writing the first Byte or Word). IL CY7C09569V CY7C09579V A n n+1 n+1 1st 2nd Cycle Cycle n+1 t CD2 n 2nd Cycle 1st Cycle level IH Page [+] Feedback ...

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... CD2 SC CKHZ CKLZ [18, 19, 20, 21, 22] NO MATCH t CD1 NO MATCH t CWDD VALID , CNTRST = for the left port, which is being written to. IH CY7C09569V CY7C09579V CD2 CKHZ CKLZ CD2 CKHZ CD2 CKLZ t CD1 VALID >maximum specified, then data is not valid CWDD CCS Page [+] Feedback ...

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... During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity. Document #: 38-06054 Rev. *B [13, 23, 24, 25 n+1 n CD2 CKHZ Q n READ NO OPERATION CY7C09569V CY7C09579V A A n+3 n CD2 CKLZ Q WRITE READ Page n+3 [+] Feedback ...

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... Switching Waveforms (continued) Pipelined Read-to-Write-to-Read (OE Controlled) t CYC2 t t CH2 CL2 CLK R ADDRESS DATA IN DATA OUT OE Document #: 38-06054 Rev. *B [11, 23, 24, 25 n+1 n+2 n n+2 n+3 t CD2 OHZ READ WRITE CY7C09569V CY7C09579V A A n+4 n CKLZ CD2 Q n+4 READ Page [+] Feedback ...

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... CKHZ t CD2 2nd Word 1st Word D D n+2 n WRITE WRITE READ Operation 2nd Cycle 1st Cycle 2nd Cycle CY7C09569V CY7C09579V n+3 n+4 n+3 n+4 2nd Word 1st Word Q Q n+3 n+3 t CD2 t DC READ READ READ 2nd Cycle 1st Cycle ...

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... OUT OE Document #: 38-06054 Rev. *B [11, 13, 14, 15, 24, 25 n+1 n+2 n n+2 t CD1 Q n+1 t CKHZ NO READ OPERATION [11 , 13, 23, 24, 25 n+1 n+2 n n+2 n OHZ READ WRITE CY7C09569V CY7C09579V n+3 n CD1 CD1 Q n CKLZ DC WRITE READ A A n+4 n CD1 t CD1 Q n CKLZ DC READ Page [+] Feedback ...

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... Document #: 38-06054 Rev. *B [11, 14, 15, 16, 24, 25, 26 n+1 n+1 n n+1 n+1 2nd Word 1st Word t CKHZ Q n 2nd Word No WRITE WRITE Operation 1st Cycle 2nd Cycle CY7C09569V CY7C09579V n+1 n+1 n CD1 CD1 Q Q n+1 n CKLZ READ READ 1st Cycle 2nd Cycle Page [+] Feedback ...

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... Note: 27 R/W = CNTRST = Document #: 38-06054 Rev. *B [27] t SAD t SCN t CD2 n+1 DC COUNTER HOLD READ WITH COUNTER [27 n+1 COUNTER HOLD READ WITH COUNTER CY7C09569V CY7C09579V t HAD t HCN Q n+2 READ WITH COUNTER t t SAD HAD t t SCN HCN Q Q n+2 n READ DC DC WITH t t ...

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... CNTRST = V IL 29. The “Internal Address” is equal to the “External Address” when ADS = CNTEN = V Document #: 38-06054 Rev. *B [28, 29 n+1 n+1 n+2 WRITE WITH WRITE COUNTER COUNTER HOLD . IH and CNTRST CY7C09569V CY7C09579V n+2 n+3 n n+3 n+4 WRITE WITH COUNTER . Page [+] Feedback ...

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... No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset. 32. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals. Ideally, DATA a valid WRITE cycle. Document #: 38-06054 Rev CD2 CKLZ READ READ ADDRESS 0 ADDRESS 1 ADDRESS A CY7C09569V CY7C09579V CD2 READ ...

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... CLK ADDRESS INTERNAL A X ADDRESS t SW R/W ADS CNTEN t t HRST SRST CNTRST t SD DATA D IN DATA OUT COUNTER RESET Document #: 38-06054 Rev. *B [23, 25, 30, 31, 32 CD1 Q 0 WRITE READ ADDRESS 0 ADDRESS 0 ADDRESS 1 CY7C09569V CY7C09579V n n READ READ ADDRESS n Page [+] Feedback ...

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... SCN HCN CA2 READ WITH t COUNTER DC [33, 34, 36] A n+1 t SAD n+1 READ WITH COUNTER is extended by 1 cycle. N CY7C09569V CY7C09579V A A n+2 n n+1 n+2 COUNTER READ WITH COUNTER HOLD A A n+3 n+2 t HAD t t HCN SCN Q Q n+2 n+3 COUNTER READ WITH COUNTER ...

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... R/W ADS CNTEN CNTRST Increment Counter Increment CY7C09569V CY7C09579V Operation [40] Deselected Write [40] Read Outputs Disabled Mode Operation Reset Counter Reset Load Address Load into Counter Hold + External Address Blocked - Read Counter Address Readout Hold External Address Blocked - Counter Disabled Page [+] Feedback ...

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... Address on 2nd I/O Pins used on 1st Cycle I/O 3L–17L I/O 3R–17R I/O 2R–17R I/O 0R–8R I/O I/O I/O 18–26 I/O 27–35 CY7C09569V CY7C09579V I/O Pins used I/O 0R–35R I/O 0R–17R I/O 0R–8R Data on 3rd Cycle Data on 4th Cycle - - - - DQ DQ 18R–26R 27R– ...

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... For a x36 format (the only active format on the left port), each address counter in the CY7C09579V uses addresses (A For the right port (allowing for the bus-matching feature), a maximum of two address bits (out of a 2-bit sub-counter) are added ...

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... Little or Big Endian operation is in effect. Document #: 38-06054 Rev. *B CY7C09569V CY7C09579V Byte (9-bit) Operation Byte (9-bit) bus sizing operation is enabled when Bus Match Select (BM) is set to a logic “1” and the Bus Size Select (SIZE) pin is set to a logic “1.” In this mode, 9 bits of data are ported through I/O ...

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... CY7C09579V-100AC CY7C09579V-100AXC CY7C09579V-100BBC 83 CY7C09579V-83AC CY7C09579V-83AXC CY7C09579V-83AI CY7C09579V-83AXI CY7C09579V-83BBC CY7C09579V-83BBI 67 CY7C09579V-67AC CY7C09579V-67BBC Document #: 38-06054 Rev. *B Package Name Package Type A144 144-Pin Thin Quad Flat Pack A144 144-Pin Pb-Free Thin Quad Flat Pack BB172 172-Ball Ball Grid Array (BGA) A144 144-Pin Thin Quad Flat Pack ...

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... Package Diagrams 144-Pin Plastic Thin Quad Flat Pack (TQFP) A144 144-Pin Pb-Free Plastic Thin Quad Flat Pack (TQFP) A144 Document #: 38-06054 Rev. *B CY7C09569V CY7C09579V 51-85047-*A Page [+] Feedback ...

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... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 172-Ball FBGA ( 1.25 mm) BB172 CY7C09569V CY7C09579V 51-85114-*B Page [+] Feedback ...

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... Document History Page Document Title: CY7C09569V/CY7C09579V 3.3 16K/ 32K x 36 FLEx36™ Synchronous Dual-Port Static RAM Document Number: 38-06054 Issue Orig. of REV. ECN NO. Date Change ** 110213 12/16/01 *A 122304 12/27/02 *B 349775 See ECN Document #: 38-06054 Rev. *B Description of Change SZV Change from Spec number: 38-00743 to 38-06054 ...