CY7C451-12JC Cypress Semiconductor Corporation., CY7C451-12JC Datasheet
CY7C451-12JC
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CY7C451-12JC Summary of contents
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... Cascadable Clocked FIFOs with Programmable and write interfaces. Both FIFOs are 9 bits wide. The CY7C451 has a 512-word by 9-bit memory array, the CY7C453 has a 2048-word by 9-bit memory array, and the CY7C454 has a 4096-word by 9-bit memory array. Devices can be cascaded to increase FIFO depth. Programmable fea- tures include Almost Full/Empty flags and generation/checking of parity ...
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... Functional Description (continued) The CY7C451, CY7C453, and CY7C454 provide three status pins to the user. These pins are decoded to determine one of six states: Empty, Almost Empty, Less than or Equal to Half Full, Greater than Half Full, Almost Full, and Full (see Table 1). The Almost Empty/Full flag (PAFE) and XO functions share the same pin ...
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... SS CC; is written into the programmable register on the rising 0 – – 8 and Q /PG/PE pins 0 – CY7C451 CY7C453 CY7C454 ) into 0 – – all other devices will have FL SS after the rising edge of CKR. Page [+] Feedback ...
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... Max., Com’l 140 = 0 mA Mil/Ind 150 = Max., Com’ Mil/Ind 80 = Max., Com’ Mil/Ind 30 Test Conditions MHz 5.0V CC CY7C451 CY7C453 CY7C454 7C451-20 7C451-30 7C453-20 7C453-30 7C454-20 7C454-30 2.4 2.4 0.4 0.4 0.4 V 2 0.8 0.5 0.8 0.5 0.8 10 +10 10 +10 10 ...
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... OE OLZ OHZ . OH is greater than t for any given device. OLZ OHZ after the clock, the decision of whether or not to include the opposite clock in the current SKEW1 CY7C451 CY7C453 CY7C454 ALL INPUT PULSES 90% 90% 10% 10% < C451-5 7C451-20 7C451-30 7C453-20 7C453-30 ...
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... SKEW2 CY7C451 CY7C453 CY7C454 7C451-20 7C451-30 7C453-20 7C453-30 7C454-20 7C454-30 Min. Max. Min. Max. Unit ...
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... HEN t t SEN [18,19,20,21] t PMR . AMR if either the first read shown did not occur or if the read occurred soon enough such that the valid OHMR CY7C451 CY7C453 CY7C454 HEN t FD C451-6 HEN t C451 MRR FIRST WRITE t MRR t AMR ...
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... WRITE t HEN t FTP t CKR t HMRP PGM READ t t CKH CKL t t SEN HEN OHP PGM WORD CY7C451 CY7C453 CY7C454 t MRR FIRST SECOND WRITE WRITE WORD 1 WORD 2 t AMR ALL DATA OUTPUTS L OW C451-9 [20,21] t MRR FIRST SECOND WRITE WRITE WORD 1 WORD 2 ...
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... FLAG READ READ UPDATE t READ SKEW2 t SKEW2 ENABLED WRITE t FD SKEW1 before R4, R4 includes W1 in the flag update and, therefore, updates FIFO to Almost Empty SKEW2 CY7C451 CY7C453 CY7C454 1 (NO CHANGE) 0 LATENTCYCLE R4 R5 FLAG ENABLED UPDATE READ READ C451-12 0 ...
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... ENABLED WRITE t FD Cycle and Update Free-Running Clocks 18 (no change) FLAG UPDATE CYCLE FLAG ENABLED UPDATE READ t SKEW2 ENABLED WRITE t FD CY7C451 CY7C453 CY7C454 ENABLED ENABLED READ READ C451-14 [22,25,27,28,29 ENABLED ENABLED READ ...
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... Notes: 30. CKW is clock and CKR is opposite clock. 31. Count = 2,049 indicates Half Full for the CY7C454, count=1,025 indicates Half Full for the CY7C453, and count = 257 indicates Half Full for the CY7C451. Values for CY7C451 count are shown in brackets. 32. When the FIFO contains 2048[1024,256] words, the rising edge of the next enabled write causes the true (LOW). ...
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... R1 R2 ENABLED ENABLED READ READ t FD 22,27,30] [ 2030 2031 [494] [495 ENABLED WRITE t SKEW2 R3 R4 ENABLED READ t FD CY7C451 CY7C453 CY7C454 2032 2033 [496] [497] 2031 2032 [495] [496 ENABLED ENABLED WRITE WRITE C451-18 2032 2033 [496] [497] W5 ...
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... FD [22,23,30,37] LATENT CYCLE 2047 [511 IGNORED IGNORED FLAG WRITE WRITE UPDATE t WRITE SKEW2 t SKEW2 ENABLED READ t FD CY7C451 CY7C453 CY7C454 [22,27,30] 2032 2033 [496] [497 ENABLED ENABLED WRITE WRITE C451-19 2048 [512 ENABLED IGNORED WRITE WRITE ...
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... PG stays HIGH. 0 – 7 Document #: 38-06033 Rev. *A [38,39] ENABLED READ t PG [38,40] ENABLED READ t PG CY7C451 CY7C453 CY7C454 DISABLED READ NEW WORD ODD NUMBER OF 1s C451-21 DISABLED READ NEW WORD EVEN NUMBER OF 1s C451-22 Page ...
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... The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at t Document #: 38-06033 Rev. *A WRITE M+2 READ M READ M+1 8 LSBs OF 8 LSBs OF WORD M-1 WORD M READ M OHZ OE t OLZ t PRT . A CY7C451 CY7C453 CY7C454 READ M LSBs OF 8 LSBs OF WORD M+1 WORD M+2 C451-23 VALID DA TA WORD M+1 C451-24 t RTR C451–25 . ...
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... Architecture The CY7C451, CY7C453, and CY7C454 consist of an array of 512/2048/4096 words of 9 bits each (implemented by an array of dual-port RAM cells), a read pointer, a write pointer, control signals (CKR, CKW, ENR, ENW, MR, OE, FL/RT, XI, XO), and flags (HF, E/F, PAFE). Resetting the FIFO Upon power-up, the FIFO must be reset with a Master Reset (MR) cycle ...
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... E/F PAFE Notes: 46 the decimal value of the binary number represented by D CY7C451 and values from for the CY7C453 and CY7C454. See Table 5 for D state CKR CKW D Q PAE CKR D Q PAF CKW ...
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... Parity Disabled (Q8 mode) When parity is disabled (or user does not program parity op- tion) the CY7C451/453/454 stores all 9 bits present on D inputs internally and will output all 9 bits on Q Generate (PG mode). Document #: 38-06033 Rev. *A Full words/locations. The Almost Full and Almost Empty flags can be programmed so that they are only ac- tive at Full and Empty boundaries ...
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... FIFOs. Depth Expansion Mode The CY7C451/453/454 can operate up to 83.3 MHz when cas- caded. Depth expansion is accomplished by connecting ex- pansion out (XO) of the first device to expansion in (XI) of the next device, with XO of the last device connected the first device ...
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... Notes: 47. Applies to both CY7C451, CY7C453, and CY7C454 operations when devices are programmed so that Almost Empty becomes active when the FIFO contains 32 or fewer words. Document #: 38-06033 Rev. *A CKR ENR – – 8 CKW CKR CY7C451/3/4 ...
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... Current AF 1 (ENR=0) Next AF 1 Write Current AF 1 (ENW=1) Next AF 1 Write Current >HF 1 (ENW=0) Next >HF 1 Write Current >HF 1 (ENW =0) Next >HF 1 Table 5. Programmable Almost Full/Almost Empty Options - CY7C451/CY7C453/CY7C454 ...
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... Ordering Information 512x9 Clocked FIFO Speed Package (ns) Ordering Code Name 12 CY7C451-12JC J65 CY7C451-12JI J65 14 CY7C451-14JC J65 CY7C451-14JI J65 20 CY7C451-20JC J65 CY7C451-20JI J65 30 CY7C451-30JC J65 CY7C451-30JI J65 2Kx9 Clocked FIFO Speed Package (ns) Ordering Code Name 12 CY7C453-12JC J65 CY7C453-12JI J65 14 CY7C453-14JC J65 CY7C453-14JI ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 32-Lead Plastic Leaded Chip Carrier J65 CY7C451 CY7C453 CY7C454 ...
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... Document Title: CY7C451, CY7C453, CY7C454 512 and Cascadable Clocked FIFOs with Program- mable Flags Document Number: 38-06033 Issue Orig. of REV. ECN NO. Date Change ** 110174 09/29/01 *A 122284 12/27/02 Document #: 38-06033 Rev. *A Description of Change SZV Change from Spec number: 38-00125 to 38-06033 RBI ...