CY7C457-12JC Cypress Semiconductor Corporation., CY7C457-12JC Datasheet

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CY7C457-12JC

Manufacturer Part Number
CY7C457-12JC
Description
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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Part Number:
CY7C457-12JC
Manufacturer:
CY
Quantity:
192
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Cypress Semiconductor Corporation
Document #: 38-06003 Rev. *A
Features
• High-speed, low-power, first-in first-out (FIFO)
• 512 x 18 (CY7C455)
• 1,024 x 18 (CY7C456)
• 2,048 x 18 (CY7C457)
• 0.65 micron CMOS for optimum speed/power
• High-speed 83-MHz operation (12 ns read/write cycle
• Low power — I
• Fully asynchronous and simultaneous read and write
• Empty, Full, Half Full, and programmable Almost Empty
• TTL compatible
• Retransmit function
• Parity generation/checking
• Output Enable (OE) pins
• Independent read and write enable pins
• Center power and ground pins for reduced noise
• Supports free-running 50% duty cycle clock inputs
• Width Expansion Capability
memories
time)
operation
and Almost Full status flags
FL/RT
Logic Block Diagram
MR
XI
CKW
RETRANSMIT
EXPANSION
CONTROL
POINTER
LOGIC
WRITE
WRITE
RESET
LOGIC
LOGIC
CC
ENW
=90 mA
Q
OUTPUT REGISTER
Q
9– 16
0 – 7
THREE–STATE
REGISTER
1024 x 18
2048 x 18
512 x 18
, Q17/PG2/PE2
ARRAY
D
, Q
PARITY
INPUT
RAM
0 – 17
8
512 x 18, 1K x 18, and 2K x 18 Cascadable
/PG1/PE1
Clocked FIFOs with Programmable Flags
3901 North First Street
OE
CKR
FLAG/PARITY
PROGRAM
REGISTER
CONTROL
POINTER
LOGIC
READ
READ
FLAG
ENR
Functional Description
The CY7C455, CY7C456, and CY7C457 are high-speed,
low-power, first-in first-out (FIFO) memories with clocked read
and write interfaces. All are 18 bits wide. The CY7C455 has a
512-word memory array, the CY7C456 has a 1,024-word
memory array, and the CY7C457 has a 2,048-word memory
array. The CY7C455, CY7C456, and CY7C457 can be cas-
caded to increase FIFO depth. Programmable features in-
clude Almost Full/Empty flags and generation/checking of par-
ity. These FIFOs provide solutions for a wide variety of data
buffering needs, including high-speed data acquisition, multi-
processor interfaces, and communications buffering.
These FIFOs have 18-bit input and output ports that are con-
trolled by separate clock and enable signals. The input port is
controlled by a free-running clock (CKW) and a write enable
pin (ENW).
• Depth Expansion Capability
• 52-pin PLCC and 52-pin PQFP
c455-1
HF
E/F
PAFE/XO
Pin Configurations
XO/PAFE
San Jose
ENW
CKW
E/F
HF
D
D
D
Q
Q
Q
Q
XI
2
1
0
0
1
2
3
8
9
10
11
12
13
14
15
16
17
18
19
20
21 22 23 24 25 26 27 28 29 30 31 32 33
7 6 5 4 3 2
CA 95134
Top View
PLCC
Revised December 26, 2002
7C455
7C456
7C457
1
52 51 50 49 48 47
CY7C455
CY7C456
CY7C457
408-943-2600
46
45
44
43
42
41
40
39
38
37
36
35
34
c455-2
D
D
D
D
D
FL/RT
MR
CKR
ENR
OE
Q
Q
Q
13
14
15
16
17
17
16
15
/PG2/PE2
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Related parts for CY7C457-12JC

CY7C457-12JC Summary of contents

Page 1

... All are 18 bits wide. The CY7C455 has a 512-word memory array, the CY7C456 has a 1,024-word memory array, and the CY7C457 has a 2,048-word memory array. The CY7C455, CY7C456, and CY7C457 can be cas- caded to increase FIFO depth. Programmable features in- clude Almost Full/Empty flags and generation/checking of par- ity ...

Page 2

... Half Full, Almost Full, and Full (see Table 1). The Almost Empty/Full flag (PAFE) shares the XO pin on the CY7C455, CY7C456, and CY7C457. This flag is valid in the standalone and width-expansion configurations. In the depth expansion, this pin provides the expansion out (XO) information that is used to signal the next FIFO when it will be activated ...

Page 3

... A CY7C455 CY7C456 CY7C457 7C455/6/7–20 7C455/6/7–30 50 33 140 120 160 140 CY7C457 2,048 x 18 Yes 52-Pin PLCC/PQFP Ambient Temperature + 10% – + 10% Page [+] Feedback ...

Page 4

... and 9,10 15- /PG1/PE1 and Q /PG2/PE2 pins CY7C455 CY7C456 CY7C457 ) into all other devices will have FL tied SS is written into the programmable register and Q after the rising 0 - 9,10 15-17 Page [+] Feedback ...

Page 5

... Com’ Ind 40 Test Conditions MHz 5.0V CC [9, 10, 11, 12, 13] 3.0V R2 GND 333 3 ns c455 OHZ , t , and OLZ OHZ . OH CY7C455 CY7C456 CY7C457 7C455/6/7– 7C455/6/7– Max Min. Max Min. Max Unit 2.4 2.4 V 0.4 0.4 0 2 0.8 –0.5 0.8 –0.5 ...

Page 6

... OLZ OHZ after the clock, the decision of whether or not to include the SKEW1 before the clock, the decision of whether or not to include the opposite SKEW2 CY7C455 CY7C456 CY7C457 7C455/6/7– 7C455/6/7– ...

Page 7

... HEN t SEN [18, 19, 20, 21] t PMR . AMR if either the first read shown did not occur or if the read occurred soon enough such that the valid OHMR CY7C455 CY7C456 CY7C457 t HEN t FD c455-6 t HEN t c455 MRR FIRST WRITE t MRR t ...

Page 8

... HEN t FTP t CKR t HMRP PGM READ t t CKH CKL t t SEN HEN OHP PGM WORD CY7C455 CY7C456 CY7C457 t MRR FIRST SECOND WRITE WRITE WORD 1 WORD 2 t AMR ALL DATA OUTPUTS L OW c455-9 [20, 21] t MRR FIRST SECOND WRITE WRITE WORD 1 WORD 2 t ...

Page 9

... READ READ t SKEW2 t SKEW2 ENABLED WRITE t FD SKEW1 before R4, R4 includes W1 in the flag update and, therefore, updates FIFO to Almost Empty state CY7C455 CY7C456 CY7C457 1 (NO CHANGE) 0 LATENT CYCLE R4 R5 FLAG ENABLED UPDATE READ READ c455- ...

Page 10

... W3 W4 ENABLED WRITE WRITE (no change) FLAG UPDATE CYCLE FLAG UPDATE READ t SKEW2 ENABLED WRITE t FD CY7C455 CY7C456 CY7C457 ENABLED ENABLED READ READ c455-14 [22, 25, 27, 28, 29 ENABLED ENABLED ENABLED READ READ ...

Page 11

... Notes: 30. CKW is clock and CKR is opposite clock. 31. Count = 1,025 indicates Half Full for the CY7C446 and CY7C456. Count = 513 indicates Half Full for the CY7C447 and CY7C457. Count = 257 indicates Half Full for the CY7C448 and CY7C458. 32. When the FIFO contains 1,024 [512] [256] words, the rising edge of the next enabled write causes the true (LOW). ...

Page 12

... ENABLED WRITE t SKEW2 R3 R4 ENABLED READ t FD SKEW2 CY7C455 CY7C456 CY7C457 2032 2033 [496] [497] 2031 [1017] 2032 [1018] [495] [496 ENABLED ENABLED WRITE WRITE c455-18 2032 2033 [1018] [1019] ...

Page 13

... IGNORED IGNORED FLAG WRITE WRITE UPDATE WRITE t SKEW2 t SKEW2 ENABLED READ t FD CY7C455 CY7C456 CY7C457 [22, 27, 30] 2032 2033 [1018] [1019] [496] [497 ENABLED ENABLED WRITE WRITE c455-19 2048 2048 [1024] [1024] [512] [512] ...

Page 14

... Document #: 38-06003 Rev. *A [38, 39] ENABLED READ t PG [38, 40] ENABLED READ t PG word is shown. The example is similar for the CY7C455 CY7C456 CY7C457 DISABLED READ NEW WORD: ODD NUMBER OF 1s c455-21 DISABLED READ NEW WORD: EVEN NUMBER OF 1s c455-22 word. 9-16 Page [+] Feedback ...

Page 15

... LSBs OF 8 LSBs OF WORD M-1 WORD M READ M OHZ OE t OLZ t PRT word is shown. 0-7 . The Q word is shown. A 0-7 CY7C455 CY7C456 CY7C457 READ M+1 READ M LSBs OF 8 LSBs OF WORD M+1 WORD M+2 c455-23 VALID DA TA WORD M+1 c455–24 t RTR 42X5–21 . RTR Page [+] Feedback ...

Page 16

... CY7C457 contains 2,047 words (2,048 words 0–17 indicate Full for the CY7C457), the next write (rising edge of CKW while ENW=LOW) causes the flag pins to output a state that is decoded as Full. Since the flags denoting emptiness (Empty, Almost Empty) are ...

Page 17

... P => 1023 512 1024 for the CY7C455, D for the CY7C456, and D 0–7 0–8 CY7C455 CY7C456 CY7C457 SKEW2 7C457 Words in FIFO 0 1 => => 1024 1025 => 2047 – P 2048 – P => 2047 2048 for the CY7C457 signifies 0–9 Page [+] Feedback ...

Page 18

... Data written to the FIFO after ac- tivation of RT are transmitted also. The full depth of the FIFO can be repeatedly retransmitted. and D inputs are 17 CY7C455 CY7C456 CY7C457 Number of Words HF in FIFO Comments 1 1 Write 1 ...

Page 19

... CKR CKW CY7C455,6,7 ENW ENR HF MR E/F OE FL/RT PAFE/ CY7C455 CY7C456 CY7C457 , Q , and MR 0–17 0–17 outputs of the first device into a high-im- bus will be 0–17 bus. 0–17 during a program read. 0–7 DATA OUT Q 0– 17 FULL EMPTY c455-25 ...

Page 20

... Write (ENW = 0) Read < (ENR = 0) Read < (ENR = 1) Read (ENR = 0) Condition CY7C455 CY7C456 CY7C457 Number of words HF in FIFO Comments 1 33 Write 1 34 Write 1 33 Flag Update and Read 1 33 Ignored Read (ENR = Read (transition from <HF to AE) Page ...

Page 21

... CY7C457–14NC N52 CY7C457–14JI J69 20 CY7C457–20JC J69 CY7C457–20NC N52 CY7C457–20JI J69 30 CY7C457–30JC J69 CY7C457–30NC N52 CY7C457–30JI J69 Document #: 38-06003 Rev. *A Package Type 52-Lead Plastic Leaded Chip Carrier Commercial 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier ...

Page 22

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 52-Lead Plastic Leaded Chip Carrier J69 52-Lead Plastic Quad Flatpack N52 CY7C455 CY7C456 CY7C457 Page [+] Feedback ...

Page 23

... Document Title: CY7C455, CY7C456, CY7C457 512 X 18 and Cascadable Clocked Fifo’s with Pro- grammable Flags Document Number: 38-06003 Issue Orig. of REV. ECN NO. Date Change ** 106464 07/11/01 *A 122256 12/26/02 Document #: 38-06003 Rev. *A Description of Change SZV Change from Spec Number: 38-00211 to 38-06003 ...

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