IMIC9835CY Cypress Semiconductor Corporation., IMIC9835CY Datasheet

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IMIC9835CY

Manufacturer Part Number
IMIC9835CY
Description
Manufacturer
Cypress Semiconductor Corporation.
Datasheet
Cypress Semiconductor Corporation
Document #: 38-07303 Rev. **
Features
Table 1. Function Table
Note:
1.
2.
• Meets Intel’s Mobile 133.3MHz Chipset
• Three CPU Clocks (66.6/100/133.3 MHz, 2.5V)
• Six SDRAM Clocks, 1-DCLK (100/133.3 MHz, 3.3V)
• Seven PCI Clocks (33MHz, 3.3V), one free running
• Two IOAPIC clocks, synchronous to CPU clock (33.3
• One REF Clock
• Two 48-MHz fixed non-SSCG clocks (USB and DOT)
Block Diagram
TEST#
MHz, 2.5V)
These are the frequencies that are selectable after power up using the SEL1 and SEL0 hardware pins. Other frequencies may be chosen using the devices
SMBUS interface. See the expanded frequency for a complete listing of all of the availible frequencies.
Will be set to 133MHz, when SMBUS Byte3, Bit 0 is set to logic 1.
0
0
1
1
1
1
P C I _ S T P #
T E S T #
C P U _ S T P #
S E L 0 , 1
S D A T A
S C L K
X O U T
P D #
X I N
SEL1
X
X
0
0
1
1
SEL0
0
1
0
1
0
1
[1]
P L L 1
P L L 2
i 2 c - c l k
i 2 c - d a t a
R i n
t r i s t a t e
s 0
P D #
R i n
P D #
i 2 c - c l k
i 2 c - d a t a
3 6 p F
3 6 p F
CPU(0:2)
Mobile 133-MHz/3 SO-DIMM Chipset Systems
TCLK/2
100.0
133.3
133.3
Hi-Z
66.6
4 8
S D R A M
I O A P I C
3 V 6 6
C P U
P C I
SDRAM(0:5)
3901 North First Street
TCLK/2
100.0
100.0
100.0
DCLK
133.3
Hi-Z
1
1
2
3
6
3
6
2
1
[2]
[2]
[2]
V D D
V D D P
V D D P
Low-EMI Clock Generator for Intel®
V D D
V D D
V D D I
V D D C
V D D S
V D D
V D D S
3V66(0:2)
TCLK/3
I O A P I C ( 0 , 1 )
C P U ( 0 : 2 )
S D R A M ( 0 : 5 )
3 V 6 6 ( 0 : 2 )
P C I _ F
P C I ( 1 : 6 )
4 8 M ( 0 , 1 )
D C L K
Hi-Z
66.6
66.6
66.6
66.6
R E F
V C H _ C L K
• Three 3V66 clocks (66.6 MHz, 3.3V) ICH, HUBLINK, and
• One selectable frequency for VCH video channel clock
• Power management using power-down, CPU stop, and
• Three function select pins (include test-mode select)
• Cypress Spread Spectrum for best electromagnetic
• SMBUS support with readback
• 56-pin SSOP and TSSOP packages
AGP memory
(48-MHz non-SSCG, 66.6-MHz CPU-SSCG, 3.3V)
PCI stop pins
interference (EMI) reduction
Pin Configuration
PCIF(1:6)
TCLK/6
3V 66_2(A G P )
Hi-Z
33.3
33.3
33.3
33.3
San Jose
48M 1(D O T)
48M 0(U S B )
P C I_S TP #
3V 66_1
3V 66_0
P C I_F
XO U T
V D D P
A V D D
A V S S
S E L0
P C I1
P C I2
P C I3
P C I4
P C I5
P C I6
V D D
V D D
V D D
V S S
V S S
V S S
V S S
R E F
V S S
XIN
48M(0:1)
TCLK/2
Hi-Z
48
48
48
48
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
CA 95134
14.318
14.318
14.318
14.318
C
9
8
3
5
TCLK
REF
Hi-Z
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Revised April 5, 2002
IOAPIC(0:10)
V S S
IO A P IC 0
IO A P IC 1
V D D I
C P U 0
C P U 1
C P U 2
V S S
V S S
S D R A M 1
S D R A M 2
S D R A M 3
V S S
S D R A M 4
S D R A M 5
D C LK
V D D S
V C H _C LK
TE S T #
P D #
S C LK
S D A TA
S E L1
V D D C
S D R A M 0
V D D S
V D D
C P U _S TP #
TCLK/6
408-943-2600
Hi-Z
33.3
33.3
33.3
33.3
C9835

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IMIC9835CY Summary of contents

Page 1

Mobile 133-MHz/3 SO-DIMM Chipset Systems Features • Meets Intel’s Mobile 133.3MHz Chipset • Three CPU Clocks (66.6/100/133.3 MHz, 2.5V) • Six SDRAM Clocks, 1-DCLK (100/133.3 MHz, 3.3V) • Seven PCI Clocks (33MHz, 3.3V), one free running • Two IOAPIC clocks, ...

Page 2

Pin Description Pin Name 1 REF 3 XIN 4 XOUT 49, 50, 52 CPU(0: 3V66(0:2) 12 PCI_F 13, 15, 16, 18, PCI (1:6) 19, 20 25, 26 48M(0,1) 36 VCH_CLK 34 CPU_STP# 11 PCI_STP# ...

Page 3

Table 2. Expanded Frequency Selection (MHz) TEST# ESEL ESEL SEL ...

Page 4

Power Management Timing 0ns CPU 100 MHz 3V66 66 MHz PCI 33 MHz IOAPIC 33 MHz PD# SDRAM 100 MHz REF 14.3 MHz VCH_CLK , 48M (0,1) Table 3. Power Management Current Conditions Power-down (PD# = LOW) CPU = 66 ...

Page 5

CPU(1,2) PCI_F CPU_STP# CPU0 PCI_STP# (High) PWR_DWN# (High) PCI_F PCI_STP# PCI(1:6) CPU_STP# (High) PD# (High) Note: 10. All the internal timing is referenced to the CPU clock 11. PCI_STP# signal is an input signal that must be made synchronous to ...

Page 6

Clock Phase 0ns CPU CLOCK 66MHz 100MHz CPU CLOCK 133MHz CPU CLOCK DCLK/SDRAM CLOCK 100MHz 0ns DCLK/SDRAM CLOCK 133MHz 3V66 CLOCK 66MHz 1.5ns~3.5 33MHz PCI CLOCK IOAPIC CLOCK 33MHz Table 4. Group Timing Relationships and Tolerances CPU to SDRAM/DCLK CPU ...

Page 7

Table 4. Group Timing Relationships and Tolerances (continued) CPU to SDRAM/DCLK CPU to 3V66 SDRAM/DCLK to 3V66 3V66 to PCI PCI to IOAPIC 48M (0,1) 2-Wire SMBUS Control Interface The 2-wire control interface implements a read/write slave only interface according ...

Page 8

Serial Control Registers Following the acknowledge of the Address Byte, two additional bytes must be sent: 1) “Command Code “ byte 2) “Byte Count” byte. Byte 0: CPU Clock Register (1 = Enable Disable ...

Page 9

Byte 4: VCH Clock Register (1 = Enable Disable Bit @Pup Pin# VCH_CLK SSC Mode Enable “0” MHZ (non-SSCG) “1” = 66.6 MHz (SSCG applicable when Byte ...

Page 10

Downspread Spread Spectrum Selection Tables Table 5. (I²C BYTE 5 Bit 7=0), Down Spread I²C Byte 5 Bit Note: 19. Buffer is 7407 with V @ 5.0V. CC Document #: ...

Page 11

Maximum Ratings Maximum Input Voltage Relative to V Maximum Input Voltage Relative to V Storage Temperature: ................................– 150 C Operating Temperature: .................................... +85 C Maximum ESD Protection.............................................. 2 KV Maximum Power Supply: ................................................5.5V DC ...

Page 12

AC Parameters Parameter Description CPU [25,26] TPeriod CPU(0:2) period [30] THIGH CPU(0:2) high time [31] TLOW CPU(0:2) low time CPU(0:2) rise and fall times TSKEW CPU0 to any CPU Skew TCCJ CPU(0:2) Cycle to Cycle Jitter SDRAM ...

Page 13

AC Parameters (continued) Parameter Description [31] TLOW PCI(_F, 1:6) low time PCI(_F, 1:6) rise and fall times TSKEW (Any PCI) to (Any PCI) Skew TCCJ PCI(_F, 1:6) Cycle to Cycle Jitter DOT and USB TPeriod DOT and ...

Page 14

Output Buffer Characteristics Table 8. CPU, IOAPIC Parameter Description IOH Pull-up Current 1 IOH Pull-up Current 2 IOL Pull-down Current 1 IOL Pull-down Current 2 Z0 Output Impedance Table 9. PCI, 3V66, VCH Parameter Description IOH Pull-up Current 1 IOH ...

Page 15

Test Measurement Condition 3.3V signals tDC - 3.3V 2.4V 1.5V 0. Table 12. Suggested Oscillator Crystal Parameters Parameter Description F Frequency o T Tolerance C T Frequency Stability S Operating Mode C Load Capacitance XTAL R Effective Series ...

Page 16

... Ordering Information Part Number IMIC9835CY 56-pin Shrunk Small Outlie package (SSOP) IMIC9835CYT 56-pin Shrunk Small Outlie package (SSOP)–Tape and Reel IMIC9835CT 56-pin Thin Shrunk Small Outlie package (TSSOP) IMIC9835CTT 56-pin Thin Shrunk Small Outlie package (TSSOP)–Tape and Reel Commercial ...

Page 17

Package Diagrams (continued) 2 Purchase components from Cypress, or one of its sublicensed Associated Companies, conveys a license under the Philips Patent Rights to use these components defined by Philips. ...

Page 18

Document Title: C9835 Low-EMI Clock Generator for Intel Document Number: 38-07373 Issue REV. ECN NO. Date ** 113556 05/28/02 Document #: 38-07303 Rev. ** ® Mobile 133-MHz/3 SO-DIMM Chipset Systems Orig. of Change Description of Change DMG New Data Sheet ...

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