CY7C1011BV33-12ZC Cypress Semiconductor Corporation., CY7C1011BV33-12ZC Datasheet

no-image

CY7C1011BV33-12ZC

Manufacturer Part Number
CY7C1011BV33-12ZC
Description
128K x 16 static RAM, 12ns
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C1011BV33-12ZC
Manufacturer:
CYPRESS
Quantity:
37
Cypress Semiconductor Corporation
Document #: 38-05021 Rev. *A
Features
Functional Description
The CY7C1011BV33 is a high-performance CMOS static
RAM organized as 131,072 words by 16 bits. This device has
an automatic power-down feature that significantly reduces
power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
• 3.0 – 3.6V Operation
• High speed
• CMOS for optimum speed/power
• Low active power
• Automatic power-down when deselected
• Independent control of upper and lower bits
• Available in 44-pin TSOP II
— t
— 684 mW (Max.)
AA
= 12, 15 ns
Logic Block Diagram
A
A
A
A
A
A
A
A
4
3
2
1
0
7
6
5
DATA IN DRIVERS
COLUMN DECODER
512 X 2048
RAM Array
128K x 16
3901 North First Street
(BLE) is LOW, then data from I/O pins (I/O
written into the location specified on the address pins (A
through A
from I/O pins (I/O
specified on the address pins (A
Reading from the device is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
will appear on I/O
then data from memory will appear on I/O
truth table at the back of this data sheet for a complete descrip-
tion of read and write modes.
The input/output pins (I/O
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1011BV33 is available in standard 44-pin TSOP
Type II package.
15
San Jose
). If Byte High Enable (BHE) is LOW, then data
1
128K x 16 Static RAM
9
to I/O
through I/O
8
. If Byte High Enable (BHE) is LOW,
1
CA 95134
through I/O
I/O
I/O
1011B-1
16
CY7C1011BV33
1
9
0
BHE
WE
CE
OE
BLE
–I/O
–I/O
) is written into the location
through A
8
16
Revised June 6, 2001
16
9
) are placed in a
1
16
to I/O
through I/O
).
408-943-2600
16
. See the
8
), is
0
[+] Feedback

Related parts for CY7C1011BV33-12ZC

CY7C1011BV33-12ZC Summary of contents

Page 1

... HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1011BV33 is available in standard 44-pin TSOP Type II package. DATA IN DRIVERS 128K x 16 RAM Array ...

Page 2

... Latch-Up Current..................................................... >200 mA Operating Range .... –0.5V to +7.0V Range Commercial +0.5V CC Industrial +0.5V CC 1011BV33-12 Test Conditions Min. = Min., 2 –4 Min 8 CY7C1011BV33 1011BV33-12 1011BV33- 190 170 10 10 Ambient [2] Temperature +70 C 3.3V 10% – +85 C 3.3V 10% 1011BV33-15 Max. Min. Max. Unit 2 ...

Page 3

... V – 0.3V < 0.3V Test Conditions MHz 5. 481 5V 3.0V R2 GND 5 pF 255 Rise Time: 1 V/ns (b) 1011B-3 167 1.73V 30 pF CY7C1011BV33 1011BV33-15 Max. Min. Max. Unit 2.2 V 0.8 –0.3 0 – – –300 –300 mA 190 170 mA 40 ...

Page 4

... AC Test Loads. Transition is measured 500 mV from steady-state voltage. HZOE HZBE HZCE HZWE Document #: 38-05021 Rev. *A 1011BV33-12 Min [ [ less than less than t , and t HZCE LZCE HZOE LZOE CY7C1011BV33 1011BV33-15 Max. Min. Max. Unit ...

Page 5

... Device is continuously selected. OE, CE, BHE and/or BHE = V 10 HIGH for read cycle. Document #: 38-05021 Rev. *A 1011BV33-12 Min [ OHA . IL CY7C1011BV33 1011BV33-15 Max. Min. Max. Unit ...

Page 6

... Data I/O is high impedance BHE and/or BLE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05021 Rev DATA VALID 50 SCE PWE CY7C1011BV33 t HZOE t HZCE t HZBE HIGH IMPEDANCE ICC CC 50% I ISB SB 1011B ...

Page 7

... WE CE DATA I/O Write Cycle No. 3 (WE Controlled, OE LOW) ADDRESS BHE, BLE DATA I/O Document #: 38-05021 Rev PWE t SCE SCE PWE HZWE SD CY7C1011BV33 1011B LZWE 1011B-10 Page [+] Feedback ...

Page 8

... Read - Lower bits only Data Out Read - Upper bits only Data In Write - All bits High Z Write - Lower bits only Data In Write - Upper bits only High Z Selected, Outputs Disabled High Z Selected, Outputs Disabled CY7C1011BV33 Mode Power Standby ( Active ( Active ( Active (I ...

Page 9

... Ordering Information Speed (ns) Ordering Code 12 CY7C1011BV33-12ZI CY7C1011BV33-12ZC 15 CY7C1011BV33-15ZC CY7C1011BV33-15ZI Package Diagrams Document #: 38-05021 Rev. *A © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user ...

Page 10

... Document Title: CY7C1011BV33 128K X 16 Static RAM Document Number: 38-05021 Issue Orig. of REV. ECN NO. Date Change ** 106652 04/26/01 MPR *A 107728 07/11/01 DFP Document #: 38-05021 Rev. *A Description of Change New Data Sheet Remove SOJ TQFP Packages. Remove 8, 10 ns. changed Low Active Power to 684. Change words/array/ added 2 addresses. ...

Related keywords