CY7C1352-100AC Cypress Semiconductor Corporation., CY7C1352-100AC Datasheet
CY7C1352-100AC
Specifications of CY7C1352-100AC
Related parts for CY7C1352-100AC
CY7C1352-100AC Summary of contents
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... The CY7C1352 is a 3.3V 256K by 18 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1352 is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle ...
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... SS V DDQ 100-Pin TQFP CY7C1352 CY7C1352 DDQ DDQ ...
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... When left floating, MODE will default HIGH to an interleaved burst order. Power supply inputs to the core of the device. Should be connected to 3.3V power supply. Power supply for the I/O circuitry. Should be connected to a 3.3V power supply. Ground for the device. Should be connected to ground of the system. 3 CY7C1352 controls DQ and [7:0] 0 ...
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... Read/Modify/Write sequences, which can be reduced to sim- ple byte write operations. Because the CY7C1352 is a common I/O device, data should not be driven into the device while the outputs are active. The Output Enable (OE) can be deasserted HIGH before present- ing data to the DQ three-state the output drivers ...
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... Burst Write Accesses The CY7C1352 has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Write operations without reasserting the address inputs. ADV/LD must be driven LOW in order to load the initial ad- dress, as described in the Single Write Access section above. ...
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... IN DDQ Max Device Deselected, or 7.0-ns cycle, 143 MHz > V – 0. DDQ 7.5-ns cycle, 133 MHz 1/t MAX CYC 10-ns cycle, 100 MHz 12.5-ns cycle, 80 MHz 6 CY7C1352 Ambient [8] Temperature DDQ +70 C 3.3V ± 5% Min. Max. Unit 3.135 3.465 3.135 3.465 2.4 0.4 2.0 V 0.3V DD ...
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... AC Test Loads and Waveforms. Test Conditions MHz 3.3V 3.3V DDQ R=317 3.3V OUTPUT 5 pF R=351 GND INCLUDING JIG AND 1352-2 SCOPE (b) Test Conditions Symbol 7 CY7C1352 Max. Unit [11] ALL INPUT PULSES 3.0V TQFP Typ. Units Notes 28 °C °C ...
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... This parameter is sampled and not 100% tested. [11,12,13] -143 Min. Max. Min. 7.0 7.5 2.0 2.5 2.0 2.5 2.0 2.0 0.5 0.5 4.0 1.5 1.5 2.0 2.0 0.5 0.5 2.0 2.0 0.5 0.5 2.0 2.0 0.5 0.5 1.7 1.7 0.5 0.5 2.0 2.0 0.5 0.5 1.5 3.5 1.5 1.5 1.5 [10, 12, 13, 14] 4.0 [10, 12, 13, 14 4.0 is less than t and t is less than t to eliminate bus contention between SRAMs when sharing the same EOLZ CHZ CLZ 8 CY7C1352 -133 -100 -80 Max. Min. Max. Min. Max. 10 12.5 3.5 4.0 3.5 4.0 2.2 2.5 0.5 1.0 4.2 5.0 7.0 1.5 1.5 2.2 2.5 0.5 1.0 2.2 2.5 0.5 1.0 2.2 2.5 0.5 1.0 2.0 2.5 0.5 1.0 2.2 2.5 0.5 1.0 3.5 1.5 3.5 1.5 5.0 1.5 1.5 4.2 5.0 7 4.2 5.0 7 ...
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... In Out Out defines a write cycle (see Write Cycle Description table). [1: and CE . All chip enables need to be active in order to select UNDEFINED = DON’T CARE 9 CY7C1352 t t CENH CENS CEN HIGH blocks all synchronous inputs RA7 t CHZ Out Out ...
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... AH AS WA2 CHZ Q1+2 Q1+3 D2 Q1+1 Out Out In Out defines a write cycle (see Write Cycle Description table). [1: and CE . All chip enables need to be active in order to select UNDEFINED = DON’T CARE 10 CY7C1352 RA3 t CLZ D2+2 D2+3 D2+1 Out input signals. [1:0] ...
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... Switching Waveforms (continued) OE Timing Ordering Information Speed (MHz) Ordering Code 143 CY7C1352-143AC 133 CY7C1352-133AC 100 CY7C1352-100AC 80 CY7C1352-80AC Document #: 38 00688 EOHZ Three-state I/O’s t EOLZ Package Name Package Type A101 100-Lead ( 1.4 mm) Thin Quad Flat Pack A101 100-Lead ( 1.4 mm) Thin Quad Flat Pack A101 100-Lead ( ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1352 51-85050-A ...