CY2210PVC-2 Cypress Semiconductor Corporation., CY2210PVC-2 Datasheet

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CY2210PVC-2

Manufacturer Part Number
CY2210PVC-2
Description
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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Cypress Semiconductor Corporation
Document #: 38-07204 Rev. *A
Intel and Pentium are registered trademarks of Intel Corporation.
• Mixed 2.5V and 3.3V Operation
• Compliant to Intel
• Multiple output clocks at different frequencies
• Spread Spectrum clocking
• Power-down features
• Three Select inputs
• Low-skew and low-jitter outputs
• OE and Test Mode support
• 56-pin SSOP package
(CY2210-2) synthesizer and driver specification
— Four CPU clocks, up to 133 MHz
— Eight synchronous PCI clocks, 1 free-running
— Two CPU/2 clocks, at one-half the CPU frequency
— Four AGP clocks at 66 MHz
— Three synchronous APIC clocks, at 16.67 MHz
— One USB clock at 48 MHz
— Two reference clocks at 14.318 MHz
— 32.5-kHz modulation frequency @ 133 MHz
— 33.1-kHz modulation frequency @ 100 MHz for
— 33.4-kHz modulation frequency @ 100 MHz for
— EPROM programmable percentage of spreading.
CY2210-02/03
CY2210-04
Default is –0.6%, which is recommended by Intel
XTALOUT
Logic Block Diagram
SPREAD
XTALIN
SEL133
CPU_STOP
PWR_DWN
PCI_STOP
SEL1
SEL0
133-MHz Spread Spectrum Clock Synthesizer/Driver
14.318
OSC.
MHz
®
CK133 (CY2210-3) & CK133W
Features
EPROM
SYS
CPU
PLL
PLL
3901 North First Street
Stop Logic
ProgDelay
EPROM-
Divider,
and
with AGP, USB, and DRCG Support
Usable with Pentium
Single-chip main motherboard clock generator
Enables reduction of EMI in some systems
Supports mobile systems
Supports up to eight CPU clock frequencies
Meets tight system timing requirements at high frequency
Enables ATE and “bed of nails” testing
Widely available, standard package enables lower cost
CPUCLK/2 [0–1] (DRCG)
REFCLK [0–1] (14.318 MHz)
CPUCLK [0–3]
PCICLK_F (33.33 MHz)
PCICLK [1–7] (33.33 MHz)
AGPCLK [0–3] (66.67 MHz)
APICCLK [0–2] (16.67 MHz)
USBCLK (48 MHz)
— Driven together, support 4 CPUs and a chipset
— Support for 4 PCI slots and chipset
— Drives up to two main memory clock generators, includ-
— Support for multiple AGP slots
— Support multiprocessing systems
— Supports USB frequencies and I/O chip
ing DRCG (CPUCLK/2)
San Jose
®
Pin Configuration
II and Pentium
PCICLK_F
Benefits
XTALOUT
AGPCLK0
AGPCLK1
AGPCLK2
AGPCLK3
REFCLK0
REFCLK1
PCICLK6
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
PCICLK7
XTALIN
V
V
SEL133
V
V
V
V
V
V
V
V
V
DDAGP
DDAGP
DDREF
SSAGP
SSAGP
SSREF
DDPCI
DDPCI
SSPCI
SSPCI
SSPCI
CA 95134
Revised December 14, 2002
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Top View
®
SSOP
III processors
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
V
APICCLK2
APICCLK1
APICCLK0
V
V
CPUCLK/2
CPUCLK/2
V
V
CPUCLK3
CPUCLK2
V
V
CPUCLK1
CPUCLK0
V
AV
AV
PCI_STOP
CPU_STOP
PWR_DWN
SPREAD
SEL1
SEL0
V
USBCLK
V
(DRCG)
(DRCG)
408-943-2600
CY2210
DDAPIC
SSAPIC
DDCPU/2
SSCPU/2
DDCPU
SSCPU
DDCPU
SSCPU
DDUSB
SSUSB
DD
SS

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CY2210PVC-2 Summary of contents

Page 1

Spread Spectrum Clock Synthesizer/Driver Features • Mixed 2.5V and 3.3V Operation ® • Compliant to Intel CK133 (CY2210-3) & CK133W (CY2210-2) synthesizer and driver specification • Multiple output clocks at different frequencies — Four CPU clocks ...

Page 2

Pin Summary Name Pins V 1 SSREF V 4 DDREF V 7, 13, 19 SSPCI V 10, 16 DDPCI V 20, 24 SSAGP V 23, 27 DDAGP V 29 SSUSB V 31 DDUSB V 40, 44 SSCPU V 43, 47 ...

Page 3

Function Table CPUCLK SEL133 SEL1 SEL0 (MHz Hi 100.227 100 100 TCLK N 133. 133.33 ...

Page 4

Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Supply Voltage ..................................................–0.5 to +7.0V Input Voltage .............................................. –0. Operating Conditions Over which Electrical Parameters are Guaranteed Parameter ...

Page 5

Switching Characteristics Parameter Output t All Output Duty Cycle 1 t CPU, CPU/2, Rising Edge Rate 2 APIC t USB, REF Rising Edge Rate 2 t PCI, AGP Rising Edge Rate 2 t CPU, CPU/2, Falling Edge Rate ...

Page 6

Switching Waveforms Duty Cycle Timing All Outputs Rise/Fall Time OUTPUT t 2 CPU-CPU Clock Skew CPUCLK CPUCLK t 6 CPU/2 - CPU/2 Clock Skew CPU/2 CPU APIC-APIC Clock Skew APIC APIC t 8 Document #: ...

Page 7

Switching Waveforms (continued) AGP-AGP Clock Skew AGP AGP t 9 PCI-PCI Clock Skew PCI PCI t 10 CPU-AGP Clock Skew CPU AGP t 11 AGP - PCI Clock Skew AGP PCI t 12 CPU-APIC Clock Skew CPU t 13 APIC ...

Page 8

Switching Waveforms (continued) CPU-PCI Clock Skew CPU t 14 PCI [7, 8] CPU_STOP Timing CPUCLK (Internal) PCICLK (Internal) PCICLK (Free-Running) CPU_STOP CPU, CPU/2, AGP (External) PCI_STOP CPUCLK (Internal) PCICLK (Internal) PCICLK (Free-Running) PCI_STOP PCICLK (External) PWR_DOWN CPUCLK (Internal) PCICLK (Internal) ...

Page 9

... Note: All capacitors must be placed as close to the pins as is physically possible. Ordering Information Ordering Code CY2210PVC-2/-3/-4 Package Diagram Document #: 38-07204 Rev. *A © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product ...

Page 10

Document Title: CY2210 133-MHz Spread Spectrum Clock Synthesizer/Driver with AGP, USB, and DRCG Support Document Number: 38-07204 Issue REV. ECN NO. Date ** 111724 01/10/02 *A 121839 12/14/02 Document #: 38-07204 Rev. *A Orig. of Change DSG Change from Spec ...

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