CY2273APVC-1 Cypress Semiconductor Corporation., CY2273APVC-1 Datasheet

CY2273APVC-1

Manufacturer Part Number

CY2273APVC-1

Description

Manufacturer

Cypress Semiconductor Corporation.

Datasheet

1.CY2273APVC-1.pdf (14 pages)

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Features

Functional Description

The CY2273A is a clock synthesizer/driver for a Pentium, Pen-

tium II, Cyrix, or AMD processor-based PC using Intel’s

82430TX, 82440LX, ALI Aladdin IV or Aladdin IV+ chipsets.

The CY2273A-1 outputs four CPU clocks at 2.5V or 3.3V with

up to 83.3MHz operation. There are seven PCI clocks, running

at 30 and 33.3MHz. One of the PCI clocks is free-running.

Additionally, the part outputs up to twelve 3.3V SDRAM clocks,

one 3.3V USB clock at 48 MHz, and one 3.3V reference clock

at 14.318 MHz. The CY2273A-2 is similar, except that

PCICLK4 and PCICLK5 are now AGP clocks. The CY2273A-3

is more suited to Pentium II systems, as it outputs one 2.5V

IOAPIC clock. Finally, the CY2273A-4 is similar to the

CY2273A-1 except that is supports 0-ns CPU-PCI delay.

Cypress Semiconductor Corporation

• Mixed 2.5V and 3.3V operation

• Complete clock solution for Pentium®, Pentium® II,

• I

• Factory-EPROM programmable output drive and slew

• Factory-EPROM programmable CPU clock frequencies

• Power-down, CPU stop and PCI stop pins

• Available in space-saving 48-pin SSOP package

Intel and Pentium are registered trademarks of Intel Corporation. I

Logic Block Diagram

Pentium®/II, 6x86, K6 Clock Synthesizer/Driver for Desktop PCs

Cyrix, and AMD processor-based motherboards

rate for EMI customization

for custom configurations

— Four CPU clocks at 2.5V or 3.3V

— Up to twelve 3.3V SDRAM clocks

— Seven synchronous PCI clocks, one free-running

— One 3.3V 48 MHz USB clock

— One 2.5V IOAPIC clock (-3 option only)

— Two AGP clocks at 60 or 66.6MHz (-2 option only)

— One 3.3V Ref. clock at 14.318 MHz

with Intel 82430TX, 82440LX or ALI IV/IV+, AGP and 3 DIMMs

C™ Serial Configuration Interface

XTALOUT

XTALIN

MODE

SDATA

CY2273A-1,-2,-4 only

SEL1

SEL0

SCLK

14.318

OSC.

MHz

INTERFACE

CONTROL

SERIAL

LOGIC

SYS PLL

EPROM

CPU

PLL

Delay (-1,-2 option)

/1 or /1.25

/1 or /2

•

3901 North First Street

STOP

LOGIC

STOP

LOGIC

C is a trademark of Philips Corporation.

CY2273A-3 only

The CY2273A possesses power-down, CPU stop, and PCI

stop pins for power management control. These inputs are

multiplexed with SDRAM clock outputs, and are selected when

the MODE pin is driven low. Additionally, the signals are syn-

chronized on-chip, and ensure glitch-free transitions on the

outputs. When the CPU_STOP input is asserted, the CPU

clock outputs are driven LOW. When the PCI_STOP input is

asserted, the PCI clock outputs (except the free-running PCI

clock) are driven LOW. When the PWR_DWN pin is asserted,

the reference oscillator and PLLs are shut down, and all out-

puts are driven LOW.

The CY2273A outputs are designed for low EMI emissions.

Controlled rise and fall times, unique output driver circuits and

factory-EPROM programmable output drive and slew-rate en-

able optimal configurations for EMI control.

CY2273A Selector Guide

Note:

CPU (60, 66.6, 75,

83.3 MHz)

CPU (60, 66.6 MHz)

SDRAM

PCI (30, 33.3MHz)

USB/IR (48MHz)

AGP (60 or 66MHz)

IOAPIC (14.318MHz)

Ref (14.318MHz)

CPU-PCI delay

Clocks Outputs

One free-running PCI clock.

PCICLK_F

USBCLK (48 MHz)

IOAPIC

REF0 (14.318 MHz)

CPUCLK [0-3]

SDRAM5/PWR_DWN

SDRAM [0-4],[8-11]

SDRAM6/CPU_STOP

SDRAM7/PCI_STOP

AGP [0,1]

PCI [0-5], PCI [0-3]

DDQ2

DDCPU

•

CY2273A-2 only

San Jose

1–5.5 ns 1–5.5 ns

•

9/12

-1

[1]

CA 95134

9/12

-2

[1]

•

October 12, 1998

CY2273A

9/12

408-943-2600

0 ns

-3

[1]

9/12

0 ns

-4

[1]

Related parts for CY2273APVC-1

CY2273APVC-1 Summary of contents

Page 1

Pentium®/II, 6x86, K6 Clock Synthesizer/Driver for Desktop PCs with Intel 82430TX, 82440LX or ALI IV/IV+, AGP and 3 DIMMs Features • Mixed 2.5V and 3.3V operation • Complete clock solution for Pentium®, Pentium® II, Cyrix, and AMD processor-based motherboards — ...

Page 2

Pin Configurations CY2273A-1,-4 SSOP Top View DDQ3 REF0 2 47 USBCLK SEL1 SS XTALIN XTALOUT CPUCLK0 V 43 DDQ3 6 CPUCLK1 PCICLK_F DDCPU ...

Page 3

Pin Summary Name Pins (-1, -4) Pins (- 14, 19, 30, 36, 6, 14, 19, 30, 36, DDQ3 N/A N/A DDQ2 DDCPU 16, 22, 27, ...

Page 4

Actual Clock Frequency Values Target Actual Frequency Frequency Clock Output (MHz) (MHz) CPUCLK 66.67 66.654 CPUCLK 60.0 60.0 CPUCLK 75.0 75.0 CPUCLK 83.33 83.138 USBCLK 48.0 48.008 • Output impedance: 25 (typical) measured at 1.5V [3] Power Management Logic - ...

Page 5

Byte 1: CPU Active/Inactive Register (1 = Active Inactive), Default = Active Bit Pin # Description Bit 7 47 (-1,-2, and -4) USBCLK 1 (-3 only) Bit 6 N/A (Reserved) drive to ‘0’ Bit 5 N/A (Reserved) drive ...

Page 6

Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Supply Voltage ..................................................–0.5 to +7.0V Input Voltage .............................................. –0. [6] Operating Conditions Parameter Analog and Digital Supply Voltage DD ...

Page 7

Switching Characteristics for CY2273A-1, CY2273A-2 Parameter Output Description t All Output Duty Cycle 1 t CPUCLK CPU Clock Rising and 2 Falling Edge Rate t SDRAM, PCI, SDRAM, PCI, REF0 2 REF0, USB Clock Rising and Fall- ing Edge Rate ...

Page 8

Switching Characteristics for CY2273A-3 Parameter Output Description t All Output Duty Cycle 1 t CPUCLK, CPU and IOAPIC Clock 2 IOAPIC Rising and Falling Edge Rate t REF0 REF0 and USBCLK Ris- 2 USBCLK ing and Falling Edge Rate t ...

Page 9

Switching Characteristics for CY2273A-4 Parameter Output Description t All Output Duty Cycle 1 t CPUCLK CPU Clock Rising and 2 Falling Edge Rate t SDRAM SDRAM, PCI, REF0, 2 PCI, REF0, USB Clock Rising and USB Falling Edge Rate t ...

Page 10

Switching Waveforms (continued) All Outputs Rise/Fall Time OUTPUT CPU-CPU Clock Skew CPUCLK CPUCLK t 5 CPU-SDRAM Clock Skew CPUCLK SDRAM t 7 CPU-PCI Clock Skew CPUCLK PCICLK t 6 PCI-PCI Clock Skew PCICLK PCICLK t 8 ...

Page 11

Switching Waveforms (continued) [11, 12] CPU_STOP CPUCLK (Internal) PCICLK (Internal) PCICLK (Free-Running) CPU_STOP CPUCLK (External) [13, 14] PCI_STOP CPUCLK (Internal) PCICLK (Internal) PCICLK (Free-Running) PCI_STOP PCICLK (External) PWR_DOWN CPUCLK (Internal) PCICLK (Internal) PWR_DWN CPUCLK (External) PCICLK (External) VCO Crystal Shaded ...

Page 12

Application Information Clock traces must be terminated with either series or parallel termination, as they are normally done. Application Circuit Summary • A parallel-resonant crystal should be used as the reference to the clock generator. The operating frequency and C ...

Page 13

... Note: All Capacitors must be placed as close to the pins as is possible Ordering Information Package Ordering Code Name CY2273APVC–1 O48 48-Pin SSOP CY2273APVC–2 O48 48-Pin SSOP CY2273APVC–3 O48 48-Pin SSOP CY2273APVC–4 O48 48-Pin SSOP Document #: 38–00615–D 0 DDCPU 0.1 F 0.1 F 0.1 F LOAD Operating Package Type Range ...

Page 14

Package Diagram © Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does ...

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