CY28312BOC-2 Cypress Semiconductor Corporation., CY28312BOC-2 Datasheet
CY28312BOC-2
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CY28312BOC-2 Summary of contents
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Features • Single-chip FTG solution for VIA™ K7 Series chipsets • Programmable clock output frequency with less than 1-MHz increment • Integrated fail-safe Watchdog timer for system recovery • Automatically switch to HW-selected or SW-programmed clock frequency when Watchdog timer ...
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Pin Definitions Pin Name Pin No. REF0/FS0 48 REF1/FS1 47 REF2 PCI_F/FS4 9 PCI_0/SEL24_48# 10 PCI1:8 11, 13, 14, 16, 17, 18, 20, 21 PCI9_E 22 AGP0:2 26, 27, 28 48MHz/FS2 6 24_48MHz/FS3 7 RST# ...
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Pin Definitions (continued) Pin Name Pin No. SDATA 31 SCLK 30 VDD_CPU 40 VDDQ_AGP 25 VDDQ_PCI 15, 23 VDDQ_48MHz 5 VDD_REF 1 VDD_Core 33 GND_REF 29, 32, 37, GND_48MHz, 43 GND_PCI, GND_AGP, GND_Core, GND_CPU Serial Data Interface The ...
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Table 1. Block Read and Block Write Protocol (continued) Block Write Protocol Bit Description ... Data Byte N/Slave Acknowledge... ... Data Byte N – 8 bits ... Acknowledge from slave ... Stop Table 2. Word Read and Word Write Protocol ...
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Table 3. Byte Read and Byte Write Protocol (continued) Byte Write Protocol Bit Description CY28312B-2 Serial Configuration Map The serial bits will be read by the clock driver in the following order: Byte 0–Bits ...
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Byte 2: Control Register 2 (continued) Bit Pin# Bit 2 13 Bit 1 11 Bit 0 10 Byte 3: Control Register Bit Pin# Bit 7 9 Bit 6 22 Bit 5 – Bit 4 21 Bit 3 46 Bit 2 ...
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Byte 6: Reserved Register (continued) Bit Name Default Bit 3 Reserved Bit 2 Reserved Bit 1 Reserved Bit 0 Reserved Byte 7: Reserved Register Bit Name Default Bit 7 Reserved Bit 6 Reserved Bit 5 Reserved Bit 4 Reserved Bit ...
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Byte 10: Skew Control Register Bit Name Bit 7 CPU_Skew2 Bit 6 CPU_Skew1 Bit 5 CPU_Skew0 Bit 4 Reserved Bit 3 PCI_Skew1 Bit 2 PCI_Skew0 Bit 1 AGP_Skew1 Bit 0 AGP_Skew0 Byte 11: Recovery Frequency N–Value Register Bit Name Default ...
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Byte 13: Programmable Frequency Select N–Value Register Bit Name Default Bit 7 CPU_FSEL_N7 Bit 6 CPU_FSEL_N6 Bit 5 CPU_FSEL_N5 Bit 4 CPU_FSEL_N4 Bit 3 CPU_FSEL_N3 Bit 2 CPU_FSEL_N2 Bit 1 CPU_FSEL_N1 Bit 0 CPU_FSEL_N0 Byte 14: Programmable Frequency Select N–Value ...
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Byte 17: Reserved Register Bit Pin# Bit 7 – Bit 6 – Bit 5 – Bit 4 – Bit 3 – Bit 2 – Bit 1 – Table 4. Additional Frequency Selections through Serial Data Interface Data Bytes Input Conditions ...
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Programmable Output Frequency, Watchdog Timer and Recovery Output Frequency Functional Description The Programmable Output Frequency feature allows users to generate any CPU output frequency from the range of 50 MHz to 248 MHz. Cypress offers the most dynamic and the ...
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Table 5. Register Summary (continued) Name WD_TIMER[4:0] These bits store the time-out value of the Watchdog timer. The scale of the timer is determine by the prescaler. The timer can support a value of 150 ms to 4.8 sec when ...
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Absolute Maximum Conditions Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other condi- tions above those specified in the ...
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DC Electrical Characteristics T A Parameter Description C Output Pin Capacitance OUT L Input Pin Inductance IN AC Electrical Characteristics T = 0°C to +70° 3.3V±5 DDQ3 XTL AC clock parameters are tested and guaranteed over ...
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AGP Clock Outputs (Lump Capacitance Test Load = 30 pF) (continued) Parameter Description t Output Skew SK f Frequency Stabilization ST from Power-up (cold start Output Impedance o REF Clock Outputs (Lump Capacitance Test Load = 20 pF) ...
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R8 CPUCLK_T 47 Clock Chip CPUDriver R9 CPUCLK_C 47 Figure 1. K7 Open Drain Clock Driver Test Circuit Ordering Information Ordering Code CY28312B-2 48-pin SSOP CY28312B-2T 48-pin SSOP–Tape and Reel Package Drawing and Dimension 48-Lead Shrunk Small Outline Package O48 ...
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Document History Page Document Title: CY28312B-2 FTG for VIA™ K7 Series Chipset with Programmable Output Frequency Document Number: 38-07596 REV. ECN NO. Issue Date ** 130574 12/04/03 Document #: 38-07596 Rev. ** Orig. of Change Description of Change RGL New ...