CY28317PVC-2 Cypress Semiconductor Corporation., CY28317PVC-2 Datasheet
CY28317PVC-2
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CY28317PVC-2 Summary of contents
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FTG for Mobile VIA™ PL133T and PLE133T Chipsets Features • Single-chip system frequency synthesizer for mobile VIA PL133T and PLE133T chipsets • Programmable clock output frequency with less than 1 MHz increment • Integrated fail-safe Watchdog Timer for system ...
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Pin Definitions Pin Name Pin No. Pin Type CPU0, CPU1 48, 47 CPUT, CPUC 44, 43 PCI2:6 13, 14, 15, 16, 17 PCI1/FS3 11 PCI0_F/FS4 10 RST# 41 48MHz/FS0 27 24_48MHz/ 26 FS1 REF1/FS2 2 REF0 3 SDRAMIN 18 SDRAM0:6 ...
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Pin Definitions (continued) Pin Name Pin No. Pin Type VDD_REF 28, 29, VDD_PCI, 35, 45 VDD_SDRAM, VDD_48MHz VDD_CPU_3.3 VDD_CPU_2.5 46 GND_REF 12, 23, GND_PCI, 32, 38, 42 GND_SDRAM, GND_48MHz, GND_CPU Table 1. Swing Select Functions Board ...
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Serial Data Interface The CY28317-2 features a two-pin, serial data interface that can be used to configure internal register settings that control particular device functions. Data Protocol The clock driver serial protocol supports byte/word Write, byte/word Read, block Write and ...
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Table 4. Word Read and Word Write Protocol Word Write Protocol Bit Description 1 Start 2:8 Slave address – 7 bits 9 Write 10 Acknowledge from slave 11:18 Command Code – 8 bits ‘1xxxxxxx’ stands for byte or word operation ...
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CY28317-2 Serial Configuration Map 1. The serial bits will be read by the clock driver in the following order: Byte 0 – Bits Byte 0: Control Register 0 Bit Pin# Bit 7 ...
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Byte 3: Control Register 3 Bit Pin# Bit 7 – Bit 6 – Bit 5 27 Bit 4 26 Bit 3 – Bit 2 31, 30 Bit 1 34, 33 Bit 0 37, 36 Byte 4: Control Register 4 Bit ...
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Byte 6: Watchdog Timer Register Bit Name Bit 7 PCI_Skew1 Bit 6 PCI_Skew0 Bit 5 WD_TIMER4 Bit 4 WD_TIMER3 Bit 3 WD_TIMER2 Bit 2 WD_TIMER1 Bit 1 WD_TIMER0 Bit 0 WD_PRE_SC ALER Byte 7: Control Register 7 Bit Pin# Bit ...
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Byte 9: System RESET and Watchdog Timer Register (continued) Bit Name Bit 5 Reserved Bit 4 RST_EN_WD Bit 3 RST_EN_FC Bit 2 WD_TO_STATU S Bit 1 WD_EN Bit 0 CPU0:1_DRV Byte 10: Skew Control Register Bit Name Bit 7 CPU0:1_Skew2 ...
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Byte 11: Recovery Frequency N-Value Register Bit Name Bit 7 ROCV_FREQ_N7 Bit 6 ROCV_FREQ_N6 Bit 5 ROCV_FREQ_N5 Bit 4 ROCV_FREQ_N4 Bit 3 ROCV_FREQ_N3 Bit 2 ROCV_FREQ_N2 Bit 1 ROCV_FREQ_N1 Bit 0 ROCV_FREQ_N0 Byte 12: Recovery Frequency M-Value Register Bit Name ...
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Byte 14: Programmable Frequency Select M-Value Register Bit Name Bit 7 Pro_Freq_EN Bit 6 CPU_FSEL_M6 Bit 5 CPU_FSEL_M5 Bit 4 CPU_FSEL_M4 Bit 3 CPU_FSEL_M3 Bit 2 CPU_FSEL_M2 Bit 1 CPU_FSEL_M1 Bit 0 CPU_FSEL_M0 Byte 15: Reserved Register Bit Pin# Bit ...
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Table 6. Additional Frequency Selections through Serial Data Interface Data Bytes Input Conditions FS4 FS3 FS2 SEL4 SEL3 SEL2 ...
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Programmable Output Frequency, Watchdog Timer and Recovery Output Frequency Functional Description The Programmable Output Frequency feature allows users to generate any CPU output frequency in the range of 50 MHz to 248 MHz. Cypress offers the most dynamic and the ...
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Table 7. Register Summary (continued) Name WD_TIMER[4:0] These bits store the time-out value of the Watchdog Timer. The scale of the timer is determine by the prescaler. The timer can support a value of 150 ms to 4.8 sec when ...
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Absolute Maximum Ratings Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions above those specified in the ...
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DC Electrical Characteristics: Parameter Description Crystal Oscillator V X1 Input Threshold Voltage TH C Load Capacitance, Imposed on LOAD [6] External Crystal C X1 Input Capacitance IN,X1 Pin Capacitance/Inductance C Input Pin Capacitance IN C Output Pin Capacitance OUT L ...
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PCI Clock Outputs, PCI (Lump Capacitance Test Load = 20 pF) Parameter Description t Period P t High Time H t Low Time L t Output Rise Edge Rate R t Output Fall Edge Rate F t Duty Cycle D ...
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... Frequency Stabilization ST from Power-up (cold start Output Impedance o Ordering Information Ordering Code CY28317PVC-2 CY28317PVC-2T CY28317ZC-2 CY28317ZC-2T Document #: 38-07094 Rev. *B Test Condition/Comments Determined by PLL divider ratio (see m/n below) (24.004 – 24)/24 (14.31818 MHz x 57/34 = 24.004 MHz) Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on the rising and falling edges at 1.5V Assumes full supply voltage reached within 1 ms from power-up ...
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Layout Diagram +3.3V Supply Document #: 38-07094 Rev DDQ3 DDQ2 10 F 0.005 ...
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Package Drawing and Dimension 48-Lead Thin Shrunk Small Outline Package, Type mm) Z48 VIA is a trademark of VIA Technologies. All product and company names mentioned in this document may be trademarks of their respective ...
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Document Title: CY28317-2 FTG for Mobile VIA PL133T and PLE133T Chipsets Document Number: 38-07094 Issue REV. ECN NO. Date ** 109867 11/13/01 *A 116450 08/16/02 *B 122779 12/26/02 Document #: 38-07094 Rev. *B Orig. of Change Description of Change IKA ...