CY2LL843ZC Cypress Semiconductor Corporation., CY2LL843ZC Datasheet

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CY2LL843ZC

Manufacturer Part Number
CY2LL843ZC
Description
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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Cypress Semiconductor Corporation
Document #: 38-07066 Rev. OBS
Features
Description
The Cypress CY2LL843 are differential line drivers and
receivers that utilize Low Voltage Signaling or LVDS, to
• ANSI TIA/EIA-644-1995-compliant
• Designed for data rates to > 700 Mbs = (350 MHz)
• Single 2 × 2 with high-drive output drivers
• Low -voltage differential signaling with output voltages
• Single 3.3V supply
• Accepts ± 350-mV differential inputs
• Output Drivers are high-impedance when disabled or
• 16-pin SOIC/TSSOP packages
• Industrial version available
of ± 350 mV into 50-ohm load version (Bus LVDS)
when V
1A
1B
2B
2A
DD
Block Diagram
@1.5V
VDD
GND
S0 S1
High-drive Two-Channel LVDS Repeater/Mux
3901 North First Street
1DE
2DE
1Z
1Y
2Y
2Z
achieve signaling rates of 700Mbs. The receiver outputs can
be switched to either or both drivers through the multiplexer
control signals S0/S1. This provides flexibility in application for
either a splitter or router configuration with a single device.
The Cypress CY2LL843 are configured as a single
two-channel repeater/Mux.
voltage of 247 mV into a 50-ohm load and receipt of as little as
100 mV signals with up to 1V of DC offset between transmitter
and receiver. The Cypress CY2LL843 doubles the output drive
current to achieve BusLVDS signaling levels with a faster
rise/fall times into 50-ohm load.
A doubly terminated BusLVDS line enables multipoint config-
urations.
Designed for both point to point based-band multi-point data
transmission over controlled impedance lines.
The LVDS standard provides a minimum differential output
San Jose
GND
1DE
1A
2A
1B
S0
2B
S1
Pin Configuration
1
2
3
4
5
6
7
8
16 pin SOIC/TSSOP
CA 95134
ComLink™ Series
Revised December 02, 2004
16
15
14
13
12
11
10
9
VDD
1Y
1Z
VDD
GND
2DE
2Z
2Y
CY2LL843
408-943-2600

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CY2LL843ZC Summary of contents

Page 1

High-drive Two-Channel LVDS Repeater/Mux Features • ANSI TIA/EIA-644-1995-compliant • Designed for data rates to > 700 Mbs = (350 MHz) • Single 2 × 2 with high-drive output drivers • Low -voltage differential signaling with output voltages of ± 350 ...

Page 2

Pin Description Pin Number Pin Name 1,2 1B 1DE 5 S1 6,7 2A 8,9 ND 10,11 2Y 2DE 14,13 IY 15,16 DD Table 1. Mux Function Table Input S0 S1 ...

Page 3

Table 4. Receiver Electrical Characteristics Over Recommended Operating Conditions Parameter VITH+ Positive-going Differential Input Voltage Threshold VITH- Negative-going Differential Input Voltage Threshold II Input Current ( A Inputs) II Input Current (B Inputs) II (Off) Power Off Current (A or ...

Page 4

Table 6. Differential Receiver to Driver Switching Characteristics Over Recommended Operating Conditions (continued) T Propagation delay, High level to High PHZ impedance output T Propagation delay, Low level to High PLZ impedance output T Propagation delay, high impedance to High ...

Page 5

Dynamic IDD CY 2LL843C VID=0.4, VIC=1.2V S0, S1=00 Temp = 25°C 45.00 43.00 41.00 39.00 37.00 35.00 33.00 31.00 29.00 27.00 25.00 50 100 150 200 Fin ( ynam 2LL843C VID =0.4, VIC ...

Page 6

V DD=3.30V , 0.500 0.400 0.300 0.200 0.100 20 120 Hz 1.280 1.270 1.260 1.250 20 120 Freq (MHz) 1Y/1Z VDD =3.30V, Temp = 25 C 60.0 40.0 ...

Page 7

V DD=3.30V , 0.500 0.400 0.300 0.200 0.100 20 120 Fre q (M Hz) 1Y Document #: 38-07066 Rev. OBS VDD= 3.30V, Temp = 120 Freq ...

Page 8

Document #: 38-07066 Rev. OBS Temp = 25°C 1 1.5 VIC Figure 9. TPHL vs. VIC 3.3V, 50 MHz Temp=85°C ...

Page 9

A Y Pulse Generator 1.4V I(A) 0.0V V I(B) 1.0V Figure 11. Test Circuit and Voltage Definitions for the Differential Output Signal A Y Pulse Generator DE 10 ...

Page 10

Application Engineering Z =50 O Pulse Generator Z =50 O Figure 15. Termination Scheme for 100-Ohm External Termination Figure 16. Termination Scheme for 100-Ohm Self-termination Interface Chip Typical Characteristics (@VDD ...

Page 11

... Ordering Information Part Number CY2LL843SI CY2LL843SIT CY2LL843ZI CY2LL843ZIT CY2LL843SC CY2LL843SCT CY2LL843ZC CY2LL843ZCT Package Drawings and Dimensions Document #: 38-07066 Rev. OBS Package Type 16-pin SOIC 16-pin SOIC–Tape and Reel 16-Pin TSSOP 16-pin TSSOP–Tape and Reel 16-pin SOIC 16-pin SOIC–Tape and Reel 16-pin TSSOP 16-pin TSSOP– ...

Page 12

Package Drawings and Dimensions 16-pin Thin Shrunk Small Outline Package (4.40 MM Body) Z16 All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07066 Rev. OBS © Cypress Semiconductor Corporation, 2002. ...

Page 13

Document Title: CY2LL843 High-drive Two-Channel LVDS Repeater/Mux Document Number: 38-07066 Issue REV. ECN No. Date ** 116745 08/01/02 *A 122751 12/14/02 OBS 294832 See ECN Document #: 38-07066 Rev. OBS Orig. of Change Description of Change CTK New Data sheet ...

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