CY7C1019V33L-12VC Cypress Semiconductor Corporation., CY7C1019V33L-12VC Datasheet

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CY7C1019V33L-12VC

Manufacturer Part Number
CY7C1019V33L-12VC
Description
128K x 8 static RAM, 12ns
Manufacturer
Cypress Semiconductor Corporation.
Datasheet
019V33
Cypress Semiconductor Corporation
Document #: 38-05150 Rev. **
Features
Functional Description
The CY7C1018V33/CY7C1019V33 is a high-performance
CMOS static RAM organized as 131,072 words by 8 bits. Easy
memory expansion is provided by an active LOW Chip Enable
(CE), an active LOW Output Enable (OE), and three-state driv-
ers. This device has an automatic power-down feature that
significantly reduces power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
• High speed
• CMOS for optimum speed/power
• Center power/ground pinout
• Automatic power-down when deselected
• Easy memory expansion with CE and OE options
Logic Block Diagram
WE
CE
OE
— t
A
A
A
A
A
A
A
A
A
AA
0
1
2
3
4
5
6
7
8
= 10 ns
INPUT BUFFER
512 x 256 x 8
DECODER
COLUMN
ARRAY
POWER
DOWN
3901 North First Street
L
7C1019V33-10
175
pins (I/O
fied on the address pins (A
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1018V33 is available in a standard 300-mil-wide
SOJ and CY7C1019V33 is available in a standard
400-mil-wide
CY7C1019V33 are functionally equivalent in all other re-
spects.
10
5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
1019V33–1
0
1
2
3
4
5
6
7
0
through I/O
San Jose
package.
7C1018V33-12
7C1019V33-12
I/O
I/O
V
V
I/O
I/O
128K x 8 Static RAM
WE
CE
CC
A
A
A
A
A
SS
A
A
A
7
7
) is then written into the location speci-
0
1
2
0
1
2
3
4
5
6
3
160
0.5
Pin Configurations
12
5
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CA 95134
through A
Top View
The
0
SOJ
Revised September 18, 2001
through I/O
CY7C1018V33
CY7C1019V33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
CY7C1018V33
16
).
7C1018V33-15
7C1019V33-15
7
A
A
A
A
OE
I/O
I/O
V
V
I/O
I/O
A
A
A
A
A
) are placed in a
16
15
14
13
SS
CC
12
11
10
9
8
408-943-2600
145
0.5
7
6
5
4
15
5
1019V33–2
and
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CY7C1019V33L-12VC Summary of contents

Page 1

Features • High speed — • CMOS for optimum speed/power • Center power/ground pinout • Automatic power-down when deselected • Easy memory expansion with CE and OE options Functional Description The CY7C1018V33/CY7C1019V33 is a ...

Page 2

Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C [1] Supply Voltage Relative GND CC DC ...

Page 3

AC Test Loads and Waveforms R1 480 3.3V 3.3V OUTPUT OUTPUT 255 INCLUDING INCLUDING JIG AND JIG AND SCOPE SCOPE (a) THÉ Equivalent to: VENIN EQUIVALENT 167 1.73V OUTPUT [4] Switching Characteristics Over the Operating Range Parameter ...

Page 4

Data Retention Characteristics Parameter Description V V for Data Retention Data Retention Current CCDR [3] t Chip Deselect to Data Retention Time CDR t Operation Recovery Time R Data Retention Waveform Switching Waveforms [9, ...

Page 5

Switching Waveforms (continued) [12, 13] Write Cycle No. 1 (CE Controlled) ADDRESS DATA I/O Write Cycle No. 2 (WE Controlled, OE HIGH During Write) ADDRESS DATA I/O NOTE 14 t HZOE ...

Page 6

... H Data Out Data High Z Ordering Information Speed (ns) Ordering Code 12 CY7C1018V33-12VC CY7C1018V33L-12VC 15 CY7C1018V33-15VC CY7C1018V33L-15VC 10 CY7C1019V33-10VC 12 CY7C1019V33-12VC CY7C1019V33L-12VC 15 CY7C1019V33-15VC CY7C1019V33L-15VC Document #: 38-05150 Rev. ** [13 SCE PWE t SD DATA VALID Mode 7 Power-Down Power-Down Read Write Selected, Outputs Disabled Package ...

Page 7

Package Diagram Document #: 38-05150 Rev. ** © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a ...

Page 8

Document Title: CY7C1018V33, CY7C1019V33 128K x 8 Static RAM Document Number: 38-05150 Issue Orig. of REV. ECN NO. Date Change ** 110185 10/21/01 SZV Document #: 38-05150 Rev. ** Description of Change Change from Spec number: 38-00637 to 38-05150 CY7C1018V33 ...

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