CY7C1217F-100AC Cypress Semiconductor Corporation., CY7C1217F-100AC Datasheet
CY7C1217F-100AC
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CY7C1217F-100AC Summary of contents
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... Supports 3.3V I/O level • Offered in JEDEC-standard 100-pin TQFP • “ZZ” Sleep Mode option [1] Functional Description The CY7C1217F is a 32,768 x 36 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is Logic Block Diagram A0, A1, A ...
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... SSQ V 27 DDQ DQP 30 D Document #: 38-05430 Rev. *A 117 MHz 100 MHz 7.5 8.0 220 205 40 40 100-Pin TQFP CY7C1217F CY7C1217F Unit DQP DDQ 76 V SSQ BYTE B B ...
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... Read cycle. The direction of the pins is controlled When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQP three-state condition. Power supply inputs to the core of the device. Ground for the core of the device. CY7C1217F , CE , and CE are 1 2 ...
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... Maximum access delay from the clock rise ( 7.5 ns (117-MHz device). CDV The CY7C1217F supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486™ processors. The linear burst sequence is suited for processors that utilize a linear burst sequence ...
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... and BWE = L or GW= L. WRITE = H when all Byte Write Enable signals CY7C1217F Second Third Address Address Min. Max CYC ...
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... CY7C1217F ADV WRITE OE CLK L-H Three-State L L-H Three-State L-H Three-State ...
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... CYC IL (min.) within 200 ms. During this time V < CY7C1217F Ambient ] Temperature + 3.3V 5%/+10% CY7C1217F Min. Max. 3.135 3.135 = –4.0 mA 2.4 = 8 –0.3 5 –30 –5 –5 –300 8.0-ns cycle, 117 MHz 10-ns cycle, 100 MHz 8.0-ns cycle, 117 MHz ...
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... V POWER is less than t and t is less than t to eliminate bus contention between SRAMs when sharing the same OELZ CHZ CLZ CY7C1217F TQFP Package 41.83 9.99 Max ALL INPUT PULSES V DDQ ...
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... Document #: 38-05430 Rev. *A [10, 11] Description t ADS t ADH A2 t WEH t t ADVH ADVS ADV suspends burst. t CDV t OELZ t OEHZ t DOH Q(A2 Q(A1) DON’T CARE is HIGH and CE is LOW. When CE is HIGH CY7C1217F 117 MHz 100 MHz Min. Max. Min. Max. 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 Deselect Cycle ...
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... Full width Write can be initiated by either GW LOW HIGH, BWE LOW and BW Document #: 38-05430 Rev WES WEH DH D(A2 BURST WRITE DON’T CARE UNDEFINED [A:D] CY7C1217F ADSC extends burst. t ADS t ADH A3 t WES t WEH t ADVS t ADVH ADV suspends burst D(A3) D( Extended BURST WRITE LOW ...
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... The data bus (Q) remains in High-Z following a Write cycle unless an ADSP , ADSC , or ADV cycle is performed. 19 HIGH. Document #: 38-05430 Rev WES WEH OELZ D(A3) t OEHZ t CDV Q(A4) Single WRITE DON’T CARE CY7C1217F A5 D(A5) Q(A4+1) Q(A4+2) Q(A4+3) Back-to-Back BURST READ UNDEFINED Page D(A6) WRITEs ...
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... Speed (MHz) Ordering Code 100 CY7C1217F-100AC Please contact your local Cypress sales representative for availability of 117-MHz speed grade option. Notes: 20. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 21. DQs are in High-Z when exiting ZZ sleep mode. ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1217F 51-85050-*A ...
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... Document History Page Document Title: CY7C1217F 1-Mbit (32K x 36) Flow-Through Sync SRAM Document Number: 38-05430 REV. ECN NO. Issue Date ** 200780 See ECN *A 213321 See ECN Document #: 38-05430 Rev. *A Orig. of Change Description of Change NJY New Data Sheet VBL Shaded selection guide and Characteristics table for non-active parts ...