CY7C1327F-166AC Cypress Semiconductor Corporation., CY7C1327F-166AC Datasheet
CY7C1327F-166AC
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CY7C1327F-166AC Summary of contents
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... Cypress Semiconductor Corporation Document #: 38-05216 Rev. *B 4-Mb (256K x 18) Pipelined Sync SRAM Functional Description The CY7C1327F SRAM integrates 262,144 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK) ...
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... TQFP 15 16 CY7C1327F CY7C1327F 166 MHz 133 MHz 100 MHz 3.5 4.0 4.5 240 225 205 DDQ DQP ...
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... BWE DDQ DQP MODE DDQ CY7C1327F DDQ DQP DDQ ...
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... The direction of the pins is controlled When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQP CY7C1327F Description and BWE). [A:B] and CE to select/deselect the device ...
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... All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The CY7C1327F supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486¥ ...
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... Bytes not selected during a Byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Because the CY7C1327F is a common I/O device, the Output Enable (OE) must be deserted HIGH before presenting data to the DQ inputs. Doing so will three-state the output drivers. ...
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... and BWE = WRITE = H when all Byte write enable signals ( CY7C1327F DQ ADV three-state three-state three-state three-state three-state ...
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... Max, Device DD Deselected 0. > V – 0.3V DDQ /2), undershoot: V (AC) > -2V (Pulse width less than t CYC IL (min.) within 200ms. During this time V < CY7C1327F Ambient Temperature V DD 0°C to +70°C 3.3V–5%/+10% 2.5V –5% –40°C to +85°C Min. Max. 3.135 3.6 2.375 V 2.4 2.0 0.4 0.4 2 ...
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... MHz 3.3V 3.3V DDQ R = 317: 3.3V OUTPUT 351: INCLUDING JIG AND (b) SCOPE R = 1667: 2.5V OUTPUT =1538: INCLUDING JIG AND (b) SCOPE CY7C1327F Min. Max. 105 100 All speeds TQFP BGA Package Package 41.83 47.63 9.99 11.71 TQFP BGA Package Package ALL INPUT PULSES V ...
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... V POWER is less than t and t is less than t to eliminate bus contention between SRAMs when sharing the same OELZ CHZ CLZ = 3.3V and is 1.25V when V = 2.5V on all data sheets. DDQ CY7C1327F 166 MHz 133 MHz 100 MHz 6.0 7.5 10 2.5 3.0 3 ...
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... OEV OEHZ t OELZ t DOH Q(A1) Q(A2) Q( DON’T CARE UNDEFINED is HIGH and CE is LOW. When CE is HIGH [A:B] CY7C1327F A3 Burst continued with new base address Deselect cycle t CHZ Q( Q( Q(A2) Q( Burst wraps around to its initial state BURST READ is HIGH LOW HIGH ...
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... OEHZ Data Out (Q) BURST READ Single WRITE Document #: 38-05216 Rev WES t WEH ADV suspends burst D(A2 BURST WRITE DON’T CARE UNDEFINED CY7C1327F ADSC extends burst t ADS t ADH A3 t WES t WEH t t ADVS ADVH D( D(A3 Extended BURST WRITE Page ...
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... The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC . 19 HIGH. Document #: 38-05216 Rev WES t WEH OELZ D(A3) t OEHZ Q(A2) Single WRITE DON’T CARE UNDEFINED CY7C1327F A5 D(A5) Q(A4) Q(A4+1) Q(A4+2) Q(A4+3) BURST READ A6 D(A6) Back-to-Back WRITEs Page ...
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... CY7C1327F-225AC CY7C1327F-225BGC CY7C1327F-225AI CY7C1327F-225BGI 200 CY7C1327F-200AC CY7C1327F-200BGC CY7C1327F-200AI CY7C1327F-200BGI 166 CY7C1327F-166AC CY7C1327F-166BGC CY7C1327F-166AI CY7C1327F-166BGI 133 CY7C1327F-133AC CY7C1327F-133BGC CY7C1327F-133AI CY7C1327F-133BGI Notes: 20. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 21. DQs are in high-Z when exiting ZZ sleep mode. ...
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... Document #: 38-05216 Rev. *B Package Name Package Type A101 100-Lead Thin Quad Flat Pack( 1.4mm) BG119 119-Ball BGA( 2.4mm) A101 100-Lead Thin Quad Flat Pack( 1.4mm) BG119 119-Ball BGA( 2.4mm) CY7C1327F Operating Range Commercial Industrial 51-85050*A Page ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 119-lead BGA ( 2.4 mm) BG119 CY7C1327F 51-85115-*A Page ...
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... Document History Page Document Title: CY7C1327F 4-Mb (256K x 18) Pipelined Sync SRAM Document Number: 38-05216 REV. ECN NO. Issue Date ** 119823 01/06/03 *A 123849 01/18/03 *B 200660 See ECN Document #: 38-05216 Rev. *B Orig. of Change HGK New Data Sheet AJH Added power up requirements to AC test loads and waveforms information ...