CY7C1329-133AC Cypress Semiconductor Corporation., CY7C1329-133AC Datasheet
CY7C1329-133AC
Specifications of CY7C1329-133AC
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CY7C1329-133AC Summary of contents
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... Asynchronous output enable • JEDEC-standard 100-lead TQFP pinout • “ZZ” Sleep Mode option and Stop Clock option Functional Description The CY7C1329 is a 3.3V, 64K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary cache with minimal glue logic. Logic Block Diagram ...
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... CY7C1329 7C1329-133 4.2 Commercial 325 Commercial 5 CY7C1329 DDQ 76 V SSQ BYTE1 SSQ V 70 DDQ ...
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... Ground for the I/O circuitry. Should be connected to ground of the system. Selects burst order. When tied to GND selects linear burst sequence. When tied left floating selects interleaved burst sequence. This is a strap pin and DDQ should remain static during device operation. No Connects. CY7C1329 , CE , and HIGH. ...
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... Write is conducted, only the selected bytes are written. Bytes not selected during a Byte Write operation will remain unaltered. A Synchronous self-timed Write mechanism has been provided to simplify the Write operations. Because the CY7C1329 is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQ [31:0] drivers ...
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... CY7C1329 , ADSP, and ADSC must after the ZZ input ZZREC Max. Unit CYC ns ADV OE DQ Write ...
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... X X CY7C1329 ADV OE DQ Write 1 X Hi-Z Write X X Hi-Z Write 0 X Hi-Z Write 0 X Hi-Z Write 1 X Hi-Z Write 1 X Hi-Z Write ...
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... Device Deselected, or 7.5-ns cycle, 133 MHz DD ≤ 0. > V – 0. DDQ 10-ns cycle, 100 MHz = 1/t MAX CYC , Device Deselected, DD ≥ V ≤ CY7C1329 [ DDQ 0°C to +70°C 3.3V 3.3V −5%/+10% −5%/+10% -40°C to +85°C Min. Max. Unit 3.135 3.6 V 3.135 3.6 V 2.4 V ...
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... GND R = 351Ω < 3.3 ns INCLUDING JIG AND (b) SCOPE [11,12,13] -133 Min. 7.5 1.9 1.9 1.5 0.5 1.5 1.5 0.5 1.5 0.5 1.5 0.5 1.5 0.5 1.5 0.5 1.5 0 [12, 13] [12, 13] 0 and t is less than t . EOLZ CHZ CLZ CY7C1329 Max. Unit [10] ALL INPUT PULSES 90% 90% 10% 10% < 3.3 ns (c) -100 Max. Min. Max. Unit 10 ns 3.2 ns 3.2 ns 2.5 ns 0.5 ns 4.2 5 ...
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... WDx stands for Write Data to Address X. Document #: 38-05279 Rev. *B Burst Write ADSP ignored with CE inactive CL 1 ADSC initiated Write masks ADSP UNDEFINED = DON’T CARE CY7C1329 Pipelined Write Unselected WD3 Unselected with CE 2 High-Z 3a Page [+] Feedback ...
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... Document #: 38-05279 Rev. *B Burst Read t ADSP ignored with Suspend Burst ADH masks ADSP OEHZ t DOH CLZ = DON’T CARE = UNDEFINED CY7C1329 Unselected Pipelined Read inactive 1 ADSC initiated Read RD3 Unselected with CHZ Page [+] Feedback ...
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... Burst Read t ADSP ignored with ADH RD3 masks ADSP OEHZ See Note Out Out In = DON’T CARE = UNDEFINED CY7C1329 Unselected Pipelined Read inactive 1 t DOH Out Out Out T CHZ Page [+] Feedback ...
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... All chip selects need to be active in order to select the device Document #: 38-05279 Rev CYC CH CL WD1 t ADH t CEH t WES ADSP ignored with CE HIGH Out Out In t DOH = UNDEFINED = DON’T CARE CY7C1329 WD2 WD3 WD4 t WEH D( CHZ Page [+] Feedback ...
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... I DD I/Os Three-state Ordering Information Speed (MHz) Ordering Code 133 CY7C1329-133AC 100 CY7C1329-100AC CY7C1329-100AI Notes: 20. Device must be deselected when entering ZZ mode. See Cycle Description table for all possible signal conditions to deselect the device. 21. I/Os are in three-state when exiting ZZ sleep mode. Document #: 38-05279 Rev ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1329 51-85050-*A ...
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... Document History Page Document Title: CY7C1329 64K x 32 Synchronous-Pipelined Cache RAM Document Number:38-05279 REV. ECN NO Issue Date ** 114388 03/25/02 *A 114499 04/11/02 *B 212291 See ECN Document #: 38-05279 Rev. *B Orig. of Description of changes Change DSG Changed from Spec number: 38-00561 to 38-05279 GLC Changed to 1.5 set-up VBL ...