CY7C4261-35JC Cypress Semiconductor Corporation., CY7C4261-35JC Datasheet
CY7C4261-35JC
Related parts for CY7C4261-35JC
CY7C4261-35JC Summary of contents
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... FIFO on each WCLK cycle. The output port is controlled in a similar manner by a free-running read clock (RCLK) and two read enable pins (REN1, REN2). In addition, the CY7C4261/71 has an output enable pin (OE). The read (RCLK) and write (WCLK) clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications ...
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... Functional Description (continued) The CY7C4261/71 provides four status pins: Empty, Full, Programmable Almost Empty, and Programmable Almost Full. The Almost Empty/Almost Full flags are programmable to single word granularity. The programmable flags default to Empty + 7 and Full – 7. The flags are synchronous, i.e., they change state relative to either the read clock (RCLK) or the write clock (WCLK) ...
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... Density 16K × 9 Package 32-pin PLCC,TQFP Architecture The CY7C4261/71 consists of an array of 16K to 32K words of nine bits each (implemented by a dual-port array of SRAM cells), a read pointer, a write pointer, control signals (RCLK, WCLK, REN1, REN2, WEN1, WEN2, RS), and flags (EF, PAE, PAF, FF). ...
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... FF). The partial status flags (PAE and PAF) can be detected from any one device. Figure 2 demonstrates a 18-bit word width by using two CY7C4261/71s. Any word width can be attained by adding additional CY7C4261/71s. When the CY7C4261/ Width-Expansion Configu- ration, the Read Enable (REN2) control input can be grounded (see Figure 2) ...
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... Figure 2. Block Diagram of 16K × 18/32K × 18 Deep Sync FIFO Memory Used in a Width-Expansion Configuration Document #: 38-06015 Rev. *C RESET (RS) 9 CY7C4261/ Read Enable 2 (REN2) CY7C4261 CY7C4271 READ CLOCK (RCLK) READ ENABLE 1 (REN1) OUTPUT ENABLE (OE) PROGRAMMABLE(PAE) EMPTY FLAG (EF) #1 EMPTY FLAG (EF) #2 DATA OUT (Q) 9 ...
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... Com’l 35 Ind/Mil 40 Com’l 10 Ind/Mil 15 Test Conditions ° MHz 5.0V CC [10, 11] 3.0V GND R2 ≤3 ns 680Ω 1.91V . CY7C4261 CY7C4271 + 0.5V CC Ambient Temperature V CC ° ° 5V ± 10 +70 C ° ° −40 5V ± 10 +85 C ° ° −55 5V ± 10 +125 C Max ...
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... CY7C4261 CY7C4271 Min. Max. Min. Max. Unit 40 28.6 MHz ...
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... NO OPERATION t REF t REF t A VALID DATA t OE [15] t SKEW1 , then FF may not change state until the next WCLK rising edge. SKEW1 , then EF may not change state until the next RCLK rising edge. SKEW2 CY7C4261 CY7C4271 NO OPERATION NO OPERATION t OHZ Page [+] Feedback ...
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... RSR RSS t RSF t RSF t RSF [19] t FRL t REF [20 OLZ When t < minimum specification, t CLK SKEW2 SKEW2 CY7C4261 CY7C4271 [17 (maximum) = either 2 FRL CLK SKEW1 CLK Page [+] Feedback ...
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... ENH WEN2 (if applicable) [19] t FRL RCLK t SKEW1 EF REN1, REN2 LOW OE DATA IN OUTPUT REGISTER Q – Document #: 38-06015 Rev DATA WRITE 2 t ENS t ENS REF REF SKEW1 t A CY7C4261 CY7C4271 t ENH t ENH [19] t FRL t REF DATA READ Page [+] Feedback ...
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... Document #: 38-06015 Rev SKEW1 DATA WRITE t WFF DATA READ t CLKL t ENS ENH t ENS ENH Note 22 [21] t PAE t ENS CY7C4261 CY7C4271 NO WRITE [14] DATA WRITE t WFF t ENH t ENS t A NEXT DATA READ WORDS Note 23 IN FIFO t PAE t t ENS ENH ...
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... If a write is performed on this rising edge of the write clock, there will be Full − (m−1) words of the FIFO when PAF goes LOW. 25. PAF offset = m. 26. 16,384 − m words for CY7C4261, 32,768 − m words for CY7C4271. 27 the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge ...
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... V 0.80 A 0.60 −55.00 4.50 5.00 5.50 6.00 AMBIENT TEMPERATURE (°C) NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE 1.20 1.10 1. 3. MHz 0.80 −55.00 5.00 65.00 125.00 AMBIENT TEMPERATURE (°C) CY7C4261 CY7C4271 PAF OFFSET MSB PAF OFFSET PAE OFFSET MSB LSB vs. AMBIENT A = 5.0V CC 5.00 65.00 125.00 NORMALIZED SUPPLY CURRENT vs. FREQUENCY 1.75 1.50 1. 25° ...
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... Speed (ns) Ordering Code 10 CY7C4261-10AC CY7C4261-10JC CY7C4261-10AI CY7C4261-10JI CY7C4261-10JXI 15 CY7C4261-15AC CY7C4261-15JC CY7C4261-15JXC CY7C4261-15AI CY7C4261-15JI 25 CY7C4261-25AC CY7C4261-25JC CY7C4261-25AI CY7C4261-25JI 35 CY7C4261-35AC CY7C4261-35JC CY7C4261-35AI CY7C4261-35JI 32Kx9 Deep Sync FIFO Speed (ns) Ordering Code 10 CY7C4271-10AC CY7C4271-10JC CY7C4271-10AI CY7C4271-10JI 15 CY7C4271-15AC CY7C4271-15JC CY7C4271-15AI CY7C4271-15JI CY7C4271-15LMB 5962-9736101QYA 25 CY7C4271-25AC CY7C4271-25JC CY7C4271-25AI ...
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... RFF t WEF t WFF t WHF t RHF t RAE t RPE t WAF t WPF t XOL t XOH CY7C4261 CY7C4271 Subgroups 10, 11 ...
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... Package Diagrams 32-Lead Thin Plastic Quad Flatpack 7 × 7 × 1.0 mm A32 32-Lead Pb-Free Plastic Leaded Chip Carrier J65 Document #: 38-06015 Rev. *C 32-Lead Plastic Leaded Chip Carrier J65 CY7C4261 CY7C4271 51-85063-*B 51-85002-*B Page [+] Feedback ...
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... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. MIL-STD-1835 C-12 51-80068-** CY7C4261 CY7C4271 Page [+] Feedback ...
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... Document History Page Document Title: CY7C4261, CY7C4271 16K/32K X 9 Deep Synchronous FIFOs Document Number: 38-06015 REV. ECN NO. Issue Date ** 106476 09/10/01 *A 122267 12/26/02 *B 127853 08/22/03 *C See ECN 393437 Document #: 38-06015 Rev. *C Orig. of Change Description of Change SZV Changed from Spec number: 38-00658 to 38-06015 RBI Added power-up requirements Maximum Ratings Information ...