CY7C43642-10AC Cypress Semiconductor Corporation., CY7C43642-10AC Datasheet
CY7C43642-10AC
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CY7C43642-10AC Summary of contents
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... Features • High-speed, low-power, bidirectional, First-In, First-Out (FIFO) memories • 1Kx36x2 (CY7C43642) • 4Kx36x2 (CY7C43662) • 16Kx36x2 (CY7C43682) • 0.35-micron CMOS for optimum speed/power • High speed 133-MHz operation (7.5-ns read/write cycle times) Logic Block Diagram CLKA CSA Port A W/RA Control Logic ENA ...
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... GND RT2 Document #: 38-06019 Rev. *B TQFP Top View CY7C43642 CY7C43662 CY7C43682 CY7C43642 CY7C43662 CY7C43682 GND ...
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... CY7C43642/62/82 CY7C43642/62/82 -7 -10 133 100 100 100 CY7C43642 CY7C43662 120 TQFP 120 TQFP CY7C43642 CY7C43662 CY7C43682 [1] CY7C43642/62/82 -15 66 100 100 CY7C43682 16K x 36 120 TQFP Page [+] Feedback ...
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... FFB/IRB is synchronized to the LOW-to-HIGH transition of CLKB. Document #: 38-06019 Rev. *B Function [2] [2] [2] [2] outputs are in the high-impedance state when CSA is HIGH. 0–35 outputs are in the high-impedance state when CSB is HIGH. 0–35 CY7C43642 CY7C43662 CY7C43682 outputs, available for 0–35 [1] outputs, available for 0–35 [1] Page [+] Feedback ...
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... AFB) HIGH. A Master Reset also forces the Mailbox flag (MBF1, MBF2) of the parallel mailbox register HIGH. After a Master Reset, the FIFO’s Full/Input Ready flag is set HIGH after two clock cycles to begin normal operation. A Master CY7C43642 CY7C43662 CY7C43682 Page ...
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... Valid programming values for the registers range from 0 to 1023 for the CY7C43642 4095 for the CY7C43662 16383 for the CY7C43682. (See footnote #2) After all the offset registers are programmed from Port A, the Port B Full/Input Ready (FFB/IRB) is set HIGH and both FIFOs begin normal operation ...
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... Therefore, the Almost Full flag of a FIFO containing [1024/4096/16384–(Y+1)] or less words remains LOW if two cycles of its synchronizing clock have not elapsed since the read that reduced the number of CY7C43642 CY7C43662 CY7C43682 or greater after the ...
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... Programming via Port A CLKA A Outputs 0– high-impedance state X In high-impedance state CY7C43642 CY7C43662 CY7C43682 are indeterminate.) For a 9-bit bus 18–35 . (In this case, 0–8 . (In this case, A are indeterminate.) For 18–35 0–8 are indeterminate.) [4] X2 and Y2 Registers ...
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... Synchronized to CLKA CY7C43682 EFA/ORA (X2+ [16384–(Y2+)1] (16384–Y2) to 16383 H 16384 H CY7C43642 CY7C43662 CY7C43682 FIFO1 write Mail1 write None FIFO2 read None Mail2 read (set MBF2 HIGH) Port Function None None FIFO2 write Mail2 write None FIFO1 read ...
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... OL 2.0 –0 Max. – – < V < Com’l Ind Com’l Ind Test Conditions T = 25° MHz 3.3V CC CY7C43642 CY7C43662 CY7C43682 [13 5.0V ± 0.5V 5.0V ± 0.5V Max. Unit V 0 0.8 V +10 A +10 A 100 mA 100 Max. ...
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... CY7C43642/62/82 -7 Min. Max. 133 7.5 3.5 3.5 3 0– after 0 0– CY7C43642 CY7C43662 CY7C43682 90% 90% 10 90% 90% 10 CY7C43642/62/82 -10 -15 Min. Max. Min. Max. Unit 100 67 MHz 7 ...
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... Active 1 6 0–35 Active 0– 0–35 90 outputs are active and MBB is HIGH. outputs are active and MBA is HIGH. CY7C43642 CY7C43662 CY7C43682 CY7C43642/62/82 -10 -15 Max. Min. Max. Unit 7 ...
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... FS1, FS0 FFA/IRA EFB/ORB AEB AFA MBF1 Note: 21. Reset is performed in the same manner for FIFO2 to load X2 and Y2 with a preset value. Document #: 38-06019 Rev. *B [21] t RSTH t t FSH FSS t RSF t RSF t RSF t RSF t RSF CY7C43642 CY7C43662 CY7C43682 t FWS t WFF Page [+] Feedback ...
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... ENS ENH ENS [25] [25 then FFB/IRB may transition HIGH one cycle later than shown. SKEW1 = ENS DIS ENS CY7C43642 CY7C43662 CY7C43682 [23] t SKEW1 AEA Offset (X2) First Word to FIFO1 t WFF ENH t t ENS ENH Page [+] Feedback ...
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... W1 W2 [1] CLKL t t ENS ENH MDV A Previous Data [28 MDV [28] [28 ENS DIS ENS CY7C43642 CY7C43662 CY7C43682 t ENH t t ENS ENH t ENH t t ENS ENH No Operation [28 [28] W3 Page DIS DIS [+] Feedback ...
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... Mode) Note: 29. Read From FIFO2. Document #: 38-06019 Rev. *B [1] t CLKL t t ENS ENS ENH MDV A Previous Data [29 MDV [29] [29 CY7C43642 CY7C43662 CY7C43682 t ENH t t ENS ENH No Operation [29 [29] W3 Page DIS DIS [+] Feedback ...
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... CLKB cycle later than shown. Document #: 38-06019 Rev CLK t t CLKL CLKH t t [30] CLKH CLKL t t REF CLK t ENS t A CY7C43642 CY7C43662 CY7C43682 [1] t REF t ENH W1 , then the transition of ORB HIGH and load SKEW1 Page [+] Feedback ...
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... CLKA edge and rising CLKB edge is less than t Document #: 38-06019 Rev CLK t t CLKH CLKL t t [31] CLKH CLKL REF REF CLK t t ENS ENH then the transition of EFB HIGH may occur one CLKB cycle later than shown. SKEW1 CY7C43642 CY7C43662 CY7C43682 W1 Page [+] Feedback ...
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... CLKA cycle later than shown. Document #: 38-06019 Rev. *B [1] t CLK t t CLKH CLKL t t [33] CLKH CLKL t t REF CLK t ENS t A CY7C43642 CY7C43662 CY7C43682 t REF t ENH W1 , then the transition of ORA HIGH and load SKEW1 Page [+] Feedback ...
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... CLKB edge and rising CLKA edge is less than t Document #: 38-06019 Rev CLK t t CLKH CLKL t t [34] CLKH CLKL t t REF REF t CLK t t ENS ENH then the transition of EFA HIGH may occur one CLKA cycle later than shown. SKEW1 CY7C43642 CY7C43662 CY7C43682 W1 Page [+] Feedback ...
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... Document #: 38-06019 Rev. *B Next Word From FIFO1 t t [35] CLKH CLKL WFF WFF CLK t t ENS ENH t t ENH ENS FIFO1 , then IRA may transition HIGH one CLKA cycle later than shown. SKEW1 CY7C43642 CY7C43662 CY7C43682 Page [+] Feedback ...
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... Document #: 38-06019 Rev. *B Next Word From FIFO1 [36 CLKH CLKL t t WFF WFF t CLK t t ENH ENS t t ENS ENH then the transition of FFA HIGH may occur one CLKA cycle later than shown. SKEW1 CY7C43642 CY7C43662 CY7C43682 Page [+] Feedback ...
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... Document #: 38-06019 Rev. *B Next Word From FIFO2 t t [37] CLKH CLKL t t WFF t WFF CLK t t ENS ENH t t ENS ENH FIFO2 , then the transition of IRB HIGH may occur one CLKB cycle later than shown. SKEW1 CY7C43642 CY7C43662 CY7C43682 Page [+] Feedback ...
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... Document #: 38-06019 Rev. *B Next Word From FIFO2 t t [38 CLKH CLKL t t WFF WFF t CLK t t ENS ENH t t ENS ENH FIFO2 , then the transition of FFB HIGH may occur one CLKB cycle later than shown. SKEW1 CY7C43642 CY7C43662 CY7C43682 Page [+] Feedback ...
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... ENH [44] t SKEW2 t PAE (X2+1) Words in FIFO2 , then AEB may transition HIGH one CLKB cycle later than shown. SKEW2 , then AEA may transition HIGH one CLKA cycle later than shown. SKEW2 CY7C43642 CY7C43662 CY7C43682 [39, 40,2] t PAE (X1+1)Words in FIFO1 t t ENH ENS [42, 43,2] ...
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... FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 Read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO. 46 Maximum FIFO Depth 1K for the CY7C43642, 4K for the CY7C43662, and 16K for the CY7C43682. 47 the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the ...
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... FIFO1 Output Register 49. Simultaneous writing to and reading from mailbox register is not allowed. Document #: 38-06019 Rev. *B [49] t ENH t ENH t ENH t ENH PMF t ENS t t MDV PMR W1 (Remains valid in Mail1 Register after read) CY7C43642 CY7C43662 CY7C43682 t PMF t ENH t DIS Page [+] Feedback ...
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... ENS ENH PMF t t MDV PMR W1 (Remains valid in Mail2 Register after read) after the RT1 rising edge. RTR to update these flags. RTR CY7C43642 CY7C43662 CY7C43682 [49] t PMF t t ENS ENH t DIS t RSTH t RTR . RTR Page [+] Feedback ...
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... Package Package Name Type A120 120-lead Thin Quad Flat Package A120 120-lead Thin Quad Flat Package A120 120-lead Thin Quad Flat Package A120 120-lead Thin Quad Flat Package CY7C43642 CY7C43662 CY7C43682 Operating Range Commercial Commercial Commercial Operating Range Commercial Commercial Commercial ...
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... Document Title: CY7C43642, CY7C43662, CY7C43682 1K/4K/16K x36 x2 Bidirectional Synchronous FIFO Document Number: 38-06019 REV. ECN NO. Issue Date ** 106556 06/08/01 *A 117171 08/23/02 *B 122271 12/26/02 Document #: 38-06019 Rev. *B Orig. of Change Description of Change SZV Change from Spec #: 38-00698 to 38-06019 OOR Added footnote to retransmit timing Added note to retransmit section ...