CY7C43684AV-7AC Cypress Semiconductor Corporation., CY7C43684AV-7AC Datasheet
CY7C43684AV-7AC
Available stocks
Related parts for CY7C43684AV-7AC
CY7C43684AV-7AC Summary of contents
Page 1
... Features • 3.3V high-speed, low-power, bidirectional, First-In First-Out (FIFO) memories w/ bus matching capabilities • 1K × 36 × 2 (CY7C43644AV) • 4K × 36 × 2 (CY7C43664AV) • 16K × 36 × 2 (CY7C43684AV) • 0.25-micron CMOS for optimum speed/power • High-speed 133-MHz operation (7.5-ns Read/Write cycle times) • Low power — ...
Page 2
... CY7C43644AV 87 86 CY7C43664AV CY7C43684AV CY7C43644AV CY7C43664AV CY7C43684AV CLKB PRS2 GND RT1 GND ...
Page 3
... Input ESD protection is greater than 2001V, and latch-up is prevented by the use of guard rings. CY7C43644/64/84AV CY7C43644/64/84AV –7 –10 133 100 CY7C43644AV CY7C43664AV CY7C43684AV [2] CY7C43644/64/84AV –15 Unit 66.7 MHz Page [+] Feedback ...
Page 4
... EFA indicates whether or not the FIFO2 memory is empty. In the FWFT mode, the ORA function is selected. ORA indicates the presence of valid data on A available for reading. EFA/ORA is synchronized to the LOW-to-HIGH transition of CLKA. CY7C43644AV CY7C43664AV CY7C43684AV CY7C43684AV 16K × 36 × 2 128 TQFP outputs 0–35 Page [+] Feedback ...
Page 5
... When FS1/SEN is LOW, a rising edge on CLKA loads the bit present on FS0/SD into the X and Y registers. The number of bit Writes required to program the offset registers is 40 for the CY7C43644AV, 48 for the CY7C43664AV, and 56 for the CY7C43684AV. The first bit Write stores the Y-register MSB and the last bit Write stores the X-register LSB ...
Page 6
... LOW-to-HIGH transition of CLKA. The A state when W/RA is HIGH. A LOW selects a Write operation and a HIGH selects a Read operation on Port B for a LOW-to-HIGH transition of CLKB. The B state when W/RB is LOW. CY7C43644AV CY7C43664AV CY7C43684AV outputs are in the high-impedance 0–35 outputs are in the high-impedance 0–35 Page [+] Feedback ...
Page 7
... BE input is a “Don’t Care.”) Document #: 38-06025 Rev. *C CY7C43644AV CY7C43664AV CY7C43684AV A HIGH on the BE/FWFT input when the Master Reset (MRS1 and MRS2) inputs go from LOW to HIGH will select a Big Endian arrangement. When data is moving in the direction from Port A to Port B, the most significant byte (word) of the long-word written to Port A will be transferred to Port B first ...
Page 8
... FIFO output register and any FIFO reads are ignored. The Empty/Output Ready flag of a FIFO is synchronized to the port clock that reads data from its array. For both the FWFT CY7C43644AV CY7C43664AV CY7C43684AV ) lines is controlled by the Port B Chip 0–35 0–35 lines are active outputs when CSB 0– ...
Page 9
... W/RA HIGH, ENA HIGH, and MBA HIGH. If the selected Port A bus size is also 36 bits, then the usable width of the Mail1 Register employs data lines A size is 18 bits, then the usable width of the Mail1 Register CY7C43644AV CY7C43664AV CY7C43684AV [2] or greater after SKEW2 [2] or greater after the Read that reduces data to the 0< ...
Page 10
... Read and Write point- ers and are updated during a retransmit cycle. Data written to the FIFO after activation of RT1, (RT2) are transmitted also. The full depth of the FIFO can be repeatedly retransmitted. CY7C43644AV CY7C43664AV CY7C43684AV and 0–17 and B . 0–8 0– ...
Page 11
... A (e) BYTE SIZE – LITTLE ENDIAN CY7C43644AV CY7C43664AV CY7C43684AV Write to FIFO Read from FIFO 1st: Read from FIFO 2nd: Read from FIFO 1st: Read from FIFO 2nd: Read from FIFO 1st: Read from FIFO 2nd: Read from FIFO ...
Page 12
... In high-impedance state X In high-impedance state In high-impedance state In high-impedance state X Active, FIFO1 output register Active, FIFO1 output register X Active, Mail1 register Active, Mail1 register CY7C43644AV CY7C43664AV CY7C43684AV [4] X2 andY2 Registers Parallel programming via Port A Serial programming via SD Reserved Reserved ...
Page 13
... Data Written to FIFO2 9–17 0–8 27– CY7C43644AV CY7C43664AV CY7C43684AV Synchronized to CLKA AEB AFA FFA/IRA Synchronized to CLKB AEA AFB FFB/IRB ...
Page 14
... Data Written to FIFO1 27–35 18–26 9–17 0– CY7C43644AV CY7C43664AV CY7C43684AV Data Read From FIFO2 18–26 9–17 0– Data Read From FIFO1 27–35 18–26 9–17 0–8 A ...
Page 15
... <2 3.0V 8 Max < V < Commercial Industrial Commercial Industrial Test Conditions ° MHz 3. CY7C43644AV CY7C43664AV CY7C43684AV [15 3.3V ± 10% 3.3V ± 10% CY7C43644/64/84AV Min. Max. Unit 2.4 V 0 <0.5 0.8 V <10 +10 A <10 + Max ...
Page 16
... CY7C43644/ 64/84AV –7 Min. Max. 133 7.5 3.5 3.5 before 3 0–35 3 2.5 [20 after 0 0–35 0 CY7C43644AV CY7C43664AV CY7C43684AV 90% 90% 10 90% 90% 10 CY7C43644/ CY7C43644/ 64/84AV 64/84AV –10 –15 Min. Max. Min. Max. Unit 100 67 MHz ...
Page 17
... Active 1 6 0–35 Active 0–35 at High 1 5 0–35 0–35 90 outputs are active and MBB is HIGH. outputs are active and MBA is HIGH CY7C43644AV CY7C43664AV CY7C43684AV CY7C43644/ CY7C43644/ 64/84AV 64/84AV –10 –15 Min. Max. Min. Max. Unit ...
Page 18
... Master Reset is performed in the same manner for FIFO2 to load X2 and Y2 with a preset value. 25. PRS1 must be HIGH during Master Reset. Document #: 38-06025 Rev. *C [24, 25] t RSTH t FWS t t BES BEH BE FWFT t t SPMS SPMH t t FSS FSH [26, 27] t RSTH CY7C43644AV CY7C43664AV CY7C43684AV t WFF t WFF Page [+] Feedback ...
Page 19
... SKEW1 SENS SENS SEN SENH SDH SDH SDS AEA Offset (X2) LSB , then FFB/IRB may transition HIGH one cycle later than shown. SKEW1 CY7C43644AV CY7C43664AV CY7C43684AV [29] t SKEW1 AEA Offset (X2) First Word to FIFO1 t WFF t WFF t WFF Page [+] Feedback ...
Page 20
... ENS ENS [33] [33 ENS ENH t t ENS ENH t t ENS ENH ENH ENH ENS ENS [35] [35 ENS DIS ENS CY7C43644AV CY7C43664AV CY7C43684AV t t ENS ENH t t ENH ENS Page [+] Feedback ...
Page 21
... If W/RB switches from Read to Write before the assertion of CSB, t 35. Written to FIFO2. Document #: 38-06025 Rev ENS ENH t ENS t t ENS ENH ENS ENH ENH ENS ENH t ENH ENS DIS ENS CY7C43644AV CY7C43664AV CY7C43684AV t ENH t ENH t t ENS ENH Page [+] Feedback ...
Page 22
... ENH [36] Previous Data [36] [36 ENH ENS t A Read 1 Previous t A Read 1 Read 2 CY7C43644AV CY7C43664AV CY7C43684AV DIS No Operation A [36 DIS [36] W3 [37 Operation DIS Read DIS Read 3 Page [+] Feedback ...
Page 23
... Read 3 CLKL ENS ENH ENS ENH Previous Data [39 [39] [39 CY7C43644AV CY7C43664AV CY7C43684AV [38] No Operation tDIS t A Read 4 Read DIS Read 5 Read ENS ENH t No Operation DIS [ DIS [39] W3 Page ...
Page 24
... CLKB cycle later than shown. Document #: 38-06025 Rev CLK t t CLKH CLKL t t CLKH CLKL [41 REF CLK t A CY7C43644AV CY7C43664AV CY7C43684AV [40] t REF ENH W1 , then the transition of ORB HIGH and load SKEW1 Page [+] Feedback ...
Page 25
... CLKA edge and rising CLKB edge is less than t Document #: 38-06025 Rev CLK t t CLKL CLKH t t CLKH CLKL [42 REF REF t CLK ENH then the transition of EFB HIGH may occur one CLKB cycle later than shown. SKEW1 CY7C43644AV CY7C43664AV CY7C43684AV W1 Page [+] Feedback ...
Page 26
... CLKA cycle later than shown. Document #: 38-06025 Rev CLK t t CLKH CLKL t t CLKH CLKL t REF t CLK t ENS t A CY7C43644AV CY7C43664AV CY7C43684AV t REF t ENH W1 , then the transition of ORA HIGH and load SKEW1 Page [+] Feedback ...
Page 27
... CLKB edge and rising CLKA edge is less than t Document #: 38-06025 Rev CLK t t CLKH CLKL t t [45] CLKH CLKL t t REF REF t CLK ENH then the transition of EFA HIGH may occur one CLKA cycle later than shown. SKEW1 CY7C43644AV CY7C43664AV CY7C43684AV [43] W1 Page [+] Feedback ...
Page 28
... CLKB edge and rising CLKA edge is less than t Document #: 38-06025 Rev. *C Next Word From FIFO1 t t [46] CLKL CLKH t t WFF WFF t CLK t t ENS ENH ENH FIFO1 , then IRA may transition HIGH one CLKA cycle later than shown. SKEW1 CY7C43644AV CY7C43664AV CY7C43684AV [43] Page [+] Feedback ...
Page 29
... Document #: 38-06025 Rev. *C Next Word From FIFO1 t t [47] CLKH CLKL t t WFF WFF t CLK t t ENH ENS t t ENS ENH then the transition of FFA HIGH may occur one CLKA cycle later than shown. SKEW1 CY7C43644AV CY7C43664AV CY7C43684AV [43] Page [+] Feedback ...
Page 30
... Document #: 38-06025 Rev. *C Next Word From FIFO2 t t CLKH CLK t t WFF WFF t CLK t t ENS ENH t t ENH FIFO2 , then the transition of IRB HIGH may occur one CLKB cycle later than shown. SKEW1 CY7C43644AV CY7C43664AV CY7C43684AV [48] Page [+] Feedback ...
Page 31
... Document #: 38-06025 Rev. *C Next Word From FIFO2 t t [51] CLKH CLKL t t WFF WFF t CLK t t ENS ENH t t ENS ENH FIFO2 , then the transition of FFB HIGH may occur one CLKB cycle later than shown. SKEW1 CY7C43644AV CY7C43664AV CY7C43684AV [50] Page [+] Feedback ...
Page 32
... PAE ( Words in FIFO2 t ENS , then AEB may transition HIGH one CLKB cycle later than shown. SKEW2 , then AEA may transition HIGH one CLKA cycle later than shown. SKEW2 CY7C43644AV CY7C43664AV CY7C43684AV [52, 53] X1 Words in FIFO t PAE ENH ENS ENH [55, 56] ...
Page 33
... FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 Read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been Read from the FIFO. 59 Maximum FIFO Depth = 1K for the CY7C43644AV, 4K for the CY7C43664AV, and 16K for the CY7C43684AV. 60 the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the ...
Page 34
... PMF t MDV t PMR W1 (Remains valid in Mail1 Register after Read) (A are “Don’t Care” inputs). In this first case B 0–17 18–35 will be indeterminate). CY7C43644AV CY7C43664AV CY7C43684AV t PMF t t ENH ENS t DIS will have valid 0–17 (A are “Don’t Care” inputs). In 0– ...
Page 35
... PMR W1 (Remains valid in Mail2 Register after Read) (B are “Don’t Care” inputs). In this first case A 0–17 18–35 will be indeterminate). after the RT1 rising edge. RTR to update these flags. RTR CY7C43644AV CY7C43664AV CY7C43684AV [64] t PMF t t ENS ENH t DIS t RSTH t ...
Page 36
... Package Type A128 128-lead Thin Quad Flat Package A128 128-lead Thin Quad Flat Package A128 128-lead Thin Quad Flat Package A128 128-lead Thin Quad Flat Package CY7C43644AV CY7C43664AV CY7C43684AV Operating Range Commercial Commercial Commercial Operating Range Commercial Commercial Commercial Operating Range Commercial ...
Page 37
... Document Title: CY7C43644AV/CY7C43664AV/CY7C43684AV 3.3V 1K/4K/16K x36 x2 Bidirectional Synchronous FIFO with Bus Matching Document Number: 38-06025 REV. ECN NO. Issue Date Change ** 107506 05/24/01 *A 109943 02/06/02 *B 117209 08/22/02 *C 122277 12/26/02 Document #: 38-06025 Rev. *C Orig. of Description of Change KTM Change from Spec #: 38-00777 to 38-06025 FSG Preliminary to final OOR Added footnote to retransmit timing, and added note to retransmit section ...