CY7C63412-PC Cypress Semiconductor Corporation., CY7C63412-PC Datasheet

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CY7C63411/12/13 CY7C63511/12/13 CY7C63612/13 Low-speed USB Peripheral Controller Cypress Semiconductor Corporation Document #: 38-08027 Rev. ** • 3901 North First Street • San Jose CY7C63411/12/13 CY7C63511/12/13 CY7C63612/13 • CA 95134 • 408-943-2600 Revised June 4, 2002 ...

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FOR FOR 1.0 FEATURES ..................................................................................................................................... 5 2.0 FUNCTIONAL OVERVIEW ............................................................................................................. 6 3.0 PIN ASSIGNMENTS ....................................................................................................................... 8 4.0 PROGRAMMING MODEL ............................................................................................................... 8 4.1 14-bit Program Counter (PC) ........................................................................................................... 8 4.2 8-bit Accumulator (A) ....................................................................................................................... 8 4.3 8-bit Index Register (X) .................................................................................................................... ...

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FOR FOR 15.2 Interrupt Latency .......................................................................................................................... 25 15.2.1 USB Bus Reset Interrupt .................................................................................................................... 25 15.2.2 Timer Interrupt .................................................................................................................................... 25 15.2.3 USB Endpoint Interrupts ..................................................................................................................... 25 15.2.4 DAC Interrupt ...................................................................................................................................... 25 15.2.5 GPIO Interrupt .................................................................................................................................... 25 16.0 TRUTH TABLES ......................................................................................................................... 26 ...

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FOR FOR Figure 6-1. Program Memory Space with Interrupt Vector Table ......................................................... 12 Figure 7-1. Clock Oscillator On-chip Circuit .......................................................................................... 15 Figure 8-1. Watch Dog Reset (WDR) ................................................................................................... 16 Figure 9-1. Block Diagram of a GPIO Line ........................................................................................... 16 Figure ...

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... CPU clock • Internal memory — 256 bytes of RAM — 4 Kbytes of EPROM (CY7C63411, CY7C63511) — 6 Kbytes of EPROM (CY7C63412, CY7C63512, CY7C63612) — 8 Kbytes of EPROM (CY7C63413, CY7C63513, CY7C63613) • Interface can auto-configure to operate as PS2 or USB • I/O port — The CY7634XX/5XX have 24 General Purpose I/O (GPIO) pins (Port capable of sinking 7 mA per pin (typical) — ...

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... The CY7C64XX/5XX/6XX are offered with multiple EPROM options to maximize flexibility and minimize cost. The CY7C63411 and the CY7C63511 have 4 Kilobytes of EPROM. The CY7C63412, CY7C63512, and CY7C63612 have 6 Kbytes of EPROM. The CY7C63413, CY7C63513, and CY7C63613 have 8 Kbytes of EPROM. ...

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FOR FOR . Logic Block Diagram 6-MHz ceramic resonator OSC 12 MHz 6 MHz 12-MHz USB 8-bit Transceiver CPU USB EPROM SIE 4/6/8 Kbyte RAM Interrupt 256 byte Controller 12-bit GPIO Timer PORT 0 GPIO PORT 1 GPIO PORT 2 ...

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FOR FOR 3.0 Pin Assignments CY7C63411/12/13 Name I/O 40-Pin 48-Pin D+, D– I/O 1,2 1,2 P0[7:0] 15,26,16, 17,32,18, 25,17,24, 31,19,30, I/O 18,23 20,29 P1[3:0] 11,30,12, 11,38,12, 29,13,28, 37,13,36, I/O 14,27 14,35 P2 7,34,8, 7,42,8, 33,9,32, 41,9,40, I/O 10,31 10,39 P3[7:4] ...

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FOR FOR 4.4 8-bit Program Stack Pointer (PSP) During a reset, the Program Stack Pointer (PSP) is set to zero. This means the program “stack” starts at RAM address 0x00 and “grows” upward from there. Note the program stack pointer ...

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FOR FOR • array: EQU 10h • MOV X,3 • MOV A,[x+array] This would have the effect of loading A with the fourth element of the SRAM “array” that begins at address 0x10h. The fourth element would be at address ...

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FOR FOR 5.0 Instruction Set Summary MNEMONIC operand HALT ADD A,expr data ADD A,[expr] direct ADD A,[X+expr] index ADC A,expr data ADC A,[expr] direct ADC A,[X+expr] index SUB A,expr data SUB A,[expr] direct SUB A,[X+expr] index SBB A,expr data SBB ...

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FOR FOR 6.0 Memory Organization 6.1 Program Memory Organization after reset 14-bit PC Figure 6-1. Program Memory Space with Interrupt Vector Table Document #: 38-08027 Rev. ** Address 0x0000 Program execution begins here after a reset 0x0002 USB Bus Reset ...

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FOR FOR 6.2 Data Memory Organization The CY7C63612/13 microcontrollers provide 256 bytes of data RAM. In normal usage, the SRAM is partitioned into four areas: program stack, data stack, user variables and USB endpoint FIFOs as shown below: after reset ...

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FOR FOR 6.3 I/O Register Summary I/O registers are accessed via the I/O Read (IORD) and I/O Write (IOWR, IOWX) instructions. IORD reads the selected port into the accumulator. IOWR writes data from the accumulator to the selected port. Indexed ...

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FOR FOR 7.0 Clocking Clock Distribution clk1x (to USB SIE) clk2x (to Microcontroller) The XTAL and XTAL are the clock pins to the microcontroller. The user can connect a low-cost ceramic resonator OUT external oscillator can be ...

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FOR FOR 8.2 Watch Dog Reset (WDR) The Watch Dog Timer Reset (WDR) occurs when the Most Significant Bit (MSB) of the 2-bit Watch Dog Timer Register transitions from LOW to HIGH. In addition to the normal reset initialization noted ...

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FOR FOR provides “HIGH” source current when the GPIO port is configured for CMOS outputs and the output data bit is written as a “1”. Q2 and Q3 are sized to sink and source, respectively, roughly the same amount of ...

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FOR FOR 9.2 GPIO Configuration Port Every GPIO port can be programmed as inputs with internal pull-ups, open drain outputs, and traditional CMOS outputs. In ad- dition, the interrupt polarity for each port can be programmed. With positive interrupt polarity, ...

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FOR FOR 10.0 DAC Port Internal Data Bus DAC Write Internal Buffer DAC Read Interrupt Enable Interrupt Polarity The DAC port provides the CY7C63511/12/13 with 8 programmable current sink I/O pins. Writing a “1” DAC I/O pin disables ...

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FOR FOR 10.2 DAC Isink Registers Each DAC I/O pin has an associated DAC Isink register to program the output sink current when the output is driven LOW. The first Isink register (0x38h) controls the current for DAC[0], the second ...

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FOR FOR 11.3 USB Port Status and Control USB status and control is regulated by the USB Status and Control Register located at I/O address 0x1Fh as shown in Figure 11-1. This is a read/write register. All reserved bits must ...

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FOR FOR Endpoint 0 Endpoint 0 Endpoint 0 Set-up In Out Received Received Received Bits[7:5] in the endpoint 0 mode registers (EPA0) are “sticky” status bits that are set by the SIE to report the type of token that was ...

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FOR FOR 14.0 Processor Status and Control Register R/W R/W IRQ Watch Dog USB Bus Pending Reset Reset The “Run” (bit 0) is manipulated by ...

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FOR FOR 15.0 Interrupts All interrupts are maskable by the Global Interrupt Enable Register and the USB End Point Interrupt Enable Register. Writing a “1” bit position enables the interrupt associated with that bit position. During a reset, ...

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FOR FOR 15.2 Interrupt Latency Interrupt latency can be calculated from the following equation: Interrupt Latency = (Number of clock cycles remaining in the current instruction) + (10 clock cycles for the CALL instruction clock cycles for the ...

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FOR FOR 16.0 Truth Tables Table 16-1. USB Register Mode Encoding Mode Encoding Setup Disable 0000 ignore Nak In/Out accept 0001 Status Out Only 0010 accept Stall In/Out 0011 accept Ignore In/Out 0100 accept Isochronous Out ignore 0101 Status In ...

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FOR FOR Table 16-2. Decode table forTable 16-3: “Details of Modes for Differing Traffic Conditions” Properties of incoming packet Encoding End Point Mode Token count buffer Setup In Out The quality status of the DMA buffer ...

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FOR FOR Table 16-3. Details of Modes for Differing Traffic Conditions End Point Mode token count buffer dval Setup Packet (if accepting) See Table 16-1 Setup <= 10 data valid See Table 16-1 Setup > 10 ...

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FOR FOR Table 16-3. Details of Modes for Differing Traffic Conditions (continued) End Point Mode token count buffer dval Out !=2 UC valid Out > ...

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FOR FOR 18.0 DC Characteristics Fosc = 6 MHz; Operating Temperature = 0 to 70°C Parameter General V Operating Voltage CC (1) V Operating Voltage CC ( Operating Supply Current CC1 4.35V CC2 CC ...

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FOR FOR Parameter I Differential Nonlinearity lin t Current Sink Response Time sink T Tracking Ratio DAC[1:0] to DAC[7:2] ratio 19.0 Switching Characteristics Parameter Description Clock t Input Clock Cycle Time CYC t Clock HIGH Time CH t Clock LOW ...

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FOR FOR . CLOCK crs PERIOD Differential Data Lines Document #: 38-08027 Rev CYC Figure 19-1. Clock Timing 90% 90% 10% 10% ...

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... Data Lines Figure 19-4. Differential to EOP Transition Skew and EOP Width T PERIOD Differential Data Lines 20.0 Ordering Information EPROM Ordering Code Size CY7C63411- CY7C63411-PVC 4 KB CY7C63412- CY7C63412-PVC 6 KB CY7C63413- CY7C63413-PVC 8 KB CY7C63511-PVC 4 KB CY7C63512-PVC 6 KB CY7C63513-PVC 8 KB CY7C63612- ...

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FOR FOR 21.0 Package Diagrams Document #: 38-08027 Rev. ** 48-Lead Shrunk Small Outline Package O48 40-Lead (600-Mil) Molded DIP P17 CY7C63411/12/13 CY7C63511/12/13 CY7C63612/13 51-85061-*C 51-85019-A Page ...

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Package Diagrams (continued) Document #: 38-08027 Rev. ** © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied ...

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FOR FOR Document Title: CY7C63411/12/13, CY7C63511/12/13, CY7C63612/13 Low-speed USB Peripheral Controller Document Number: 38-08027 Issue REV. ECN NO. Date ** 116224 06/12/02 Document #: 38-08027 Rev. ** Orig. of Change Description of Change DSG Change from Spec number: 38-00754 to ...